Hewlett Packard Enterprise Development LP

Compaq Computer Corporation, Inc.

Hewlett-packard Development Company, L.P.

Compaq Information Technologies Group, L.p.

Brian T Purcell

Melvin K Benedict

Jay C Brinkmeyer

John P Franz

Thomas J Bonola

Steven J Dean

Barry S Basile

William F Whiteman

Zheila N Madanipour

Robert Allen Voss

David M Koonce

Chandler Ray Harris

Michael Bourg

Sompong Paul Olarig

Kevin B Leigh

Siamak Tavallaei

Harvey John Lunsman

Minh H Nguyen

Alan L Goodrum

Peter A Hansen

Michael Lawrence Sabotta

Patrick A Raymond

Steven Martin

David Paul Mohr

Michael P Moriarty

Vincent W Michna

Brian S Hausauer

B Tod Cox

Michael White

Binh Nguyen

Torsten Wilde

Robert Mascia

Harvey White, Jr

Paul Danna

Pamela M Cook

Barry L Olawsky

Mark L Hammons

Rob J Rongstad

Quoc Hung C Vu

Kyran Wilfred Fey, Jr

Charles R Hanna

Jonathan Daniel Befort

Timothy S McCann

Glenn H Lupton

A process includes communicating a coolant flow between an inlet and an outlet of a coolant subsystem that is associated with a cooling domain to remove thermal energy from a plurality of processor-based nodes of the cooling domain. The communication of the coolant flow has associated predefined parameters. The process includes regulating a temperature of the coolant flow at the outlet. In accordance with example implementations, the regulation includes determining, based on the predefined parameters, a minimum collective power consumption by the processor-based nodes to maintain a temperature of the coolant flow at the outlet at or above a minimum threshold temperature, and based on the minimum power consumption, scheduling jobs to be executed by the nodes.

Scheduling jobs for processor-based nodes to regulate coolant flow temperatures

A flexible input/output (I/O) expansion card connection and communication technique are provided. The flexible I/O expansion card is, in some examples, a mezzanine expansion card that may be a single width mezzanine expansion card, a double width expansion card, or a quad width expansion card. Multiple connectors on a mainboard provide a slot to receive plug in (insertion) of an expansion card. A slot is associated with a communication bus (e.g., Peripheral Component Interconnect (PCI)) established between the expansion card and an associated processor. The expansion card (or more than one expansion card) may be inserted in multiple orientations with respect to the multiple connectors. Automatic adjustment of communication on the communication bus may be implemented via one or more hardware level and/or software assisted translations to allow the mezzanine expansion card to function in a normal or a reverse (180 degrees relative to normal) orientation.

Flexible I/O server interface card orientation

A method and system are disclosed that allow easier coupling between high-density connectors. In one example implementation, the connectors on a computer board are mounted on flexible tabs extending from the computer board, the tabs having been formed by cutting slots on both sides of each of the tabs. A milled section within each tab makes the tab thinner, allowing it additional flexibility. In another example implementation, a pass-through connector is used as an intermediary between two mating connectors. The pass-through connector has internal pins with greater tolerance than the tolerance between the two mating connectors, allowing it easier alignment of pins for coupling. In yet another example implementation, mating connectors are coupled using a bundle of cables between the mating connectors that allows the coupling of multiple connectors, one at a time, reducing or eliminating the need to simultaneously couple multiple connectors.

High connector count mating compliance

A pseudo all-to-all connected system for optical communications are provided. A plurality of nodes are grouped into a node-division multiplexing (NDM) node. An electrical shuffle comprising a plurality of electrical traces connects each port of the plurality of nodes to at least one optical transceiver. The at least one optical transceiver is configured to multiplex a plurality of electrical signals from the plurality of nodes into a plurality of wavelength division multiplexing (WDM) optical signals, the electrical shuffle being configured to route the plurality of electrical signals from each port of the plurality of nodes to form one of a plurality of ordered sequences of signals from the plurality of nodes. A fiber shuffle is configured to route the plurality of WDM optical signals to and from a plurality of NDM connectors.

Node-division multiplexing with sub-WDM node ports for pseudo-all-to-all connected optical links

An example device in accordance with an aspect of the present disclosure includes at least one interface set, including a first interface, at least one second interface, and at least one third interface. A first portion of the first interface is coupled to a second portion of the at least one second interface. A second portion of the first interface is coupled to a first portion of the at least one third interface. The first portion of the first interface is isolated from the second portion of the first interface, the first portion of the second interface is isolated from the second portion of the second interface, and the first portion of the third interface is isolated from the second portion of the third interface.

Backplane interface sets

Example implementations relate to a heat transfer adapter plate. For example, a heat transfer adapter plate can comprise a first retention mechanism to couple a heat transfer device to the heat transfer adapter plate and a second retention mechanism to couple the heat transfer adapter plate to an electronic component. The heat transfer adapter plate can accept a plurality of heat transfer device types, including but not limited to, a passive heat exchanger, an active heat exchanger, and a heat pipe.

Heat transfer adapter plate

The present disclosure discloses an expansion bus device that is communicatively coupled to a plurality of input-output devices. The expansion bus device includes a plurality of input-output slots, via which the plurality of input-output devices are coupled to the expansion bus device. The expansion bus device also includes a retimer switch communicatively connected to each of the plurality of input-output slots. The retimer switch supports switching between the plurality of input-output slots.

Expansion bus devices comprising retimer switches

In one example implementation according to aspects of the present disclosure, a server chassis may include a server zone to receive a plurality of blade servers, each of the plurality of blade servers having a fabric connection. The server chassis may further include a flexible input/output zone to receive an input/output card, the input/output card being communicatively coupled to each of the plurality of blade servers via the fabric connection of each of the plurality of blade servers. The functionality of the input/output card may be distributed across the plurality of blade servers.

Flexible input/output zone in a server chassis

Supporting input/output (I/O) connectivity for a printed circuit assembly (PCA) in a hot aisle cabling or a cold aisle cabling arrangement includes a chassis, the chassis being connected to a rack in a data center, and a PCA slidably connected to the chassis via a tray, in which the PCA comprises a number of bill of material (BOM) options to customize the PCA and a single basic input/output system (BIOS) image, and in which the PCA is physically shifted on the chassis to accommodate a cold aisle cabling or a hot aisle cabling arrangement of the data center.

Supporting input/output (I/O) connectivity for a printed circuit assembly (PCA) in a hot aisle cabling or a cold aisle cabling arrangement

Embodiments provide apparatuses and systems in which slave power sequencers share a command bus and power sequence respective power groups through power sequence states of a power sequencing protocol in response to commands on the command bus. In some examples, a system may include a master power sequencer to output onto a command bus a command to perform a power sequencing protocol for transitioning the system from a first power state to a second power state, and a plurality of slave power sequencers sharing the command bus, each slave power sequencer to power sequence a respective power group to a next power sequence state in response to the command. Other examples are described and claimed.

Power sequencing by slave power sequencers sharing a command bus

A system in some embodiments includes a system having a memory module having a first board comprising a first plurality of memory receptacles configured to support a first plurality of in-line memory modules in an overlapping relationship with a second plurality of in-line memory modules disposed on a second board. Further, a system in some embodiments includes rotating first and second memory boards into a parallel configuration via a hinge coupling the first and second memory boards, and inserting the first and second memory boards into first and second board connectors simultaneously.

Memory system

Systems and methods for improving performance of a rentable fabric are disclosed. In an exemplary embodiment a system may comprise a plurality of compute nodes, a routable fabric, and a plurality of chipsets connected by the routable fabric to the plurality of compute nodes. The chipsets have range registers dynamically directing traffic from any device to any of the plurality of compute nodes over the routable fabric.

Systems and methods for improving performance of a routable fabric

A system and method for maintaining a communications within a computer system after a data transport failure across a first link. Fail-over capability is attained by re-establishing communications across a secondary link using different transport mechanisms. Between two Input/Output Processors (IOPs) within a computer system, such as a server, a series of data transactions therebetween are queued until transaction completion. Upon detection of a failure condition between the IOPs across the first link, the IOPs engage fail-over mechanisms to preserve uncompleted data transactions until communications are re-established across the secondary link.

System and method for fail-over data transport

A system and method for maintaining a communications within a computer system after a data transport failure across a first link. Fail-over capability is attained by re-establishing communications across a secondary link using different transport mechanisms. Between two Input/Output Processors (IOPs) within a computer system, such as a server, a series of data transactions therebetween are queued until transaction completion. Upon detection of a failure condition between the TOPs across the first link, the IOPs engage fail-over mechanisms to preserve uncompleted data transactions until communications are re-established across the secondary link.

Growing community of inventors

Tomball, TX, United States of America

Brian T Purcell