Nvidia Corporation

Brian Schieck

Howard Lee Marks

Alex Waizman

Zuhair Bokharey

Don Templeton

Jayprakash Chipalkatti

Gurpreet Shinh

Prashant Pathak

Donald E Templeton

Julie Lam

Abraham Fong Yee

Shantanu Kalchuri

An IC package including an integrated circuit die having a major surface and one or more solder bumps located on the major surface in at least one corner region of the major surface and a substrate having a surface, the surface including bump pads thereon. The major surface of the integrated circuit die faces the substrate surface, the one or more solder bumps are bonded to individual ones of the bump pads to thereby form a bond joint, the major surface of the integrated circuit die has a footprint area of at least about 400 mm. A ratio of a coefficient of thermal expansion of the substrate (CTE) to a coefficient of thermal expansion of the integrated circuit die (CTE) is at least about 3:1. A method of manufacturing an IC package is also disclosed.

IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperatures

Various embodiments relating to semiconductor package structures having reduced thickness while maintaining rigidity are provided. In one embodiment, a semiconductor package structure includes a substrate including a surface, a semiconductor die including a first interface surface connected to the surface of the substrate and a second interface surface opposing the first interface surface, a mold compound applied to the substrate surrounding the semiconductor die. The second interface surface of the semiconductor die is exposed from the mold compound. The semiconductor package structure includes a heat dissipation cover attached to the second interface surface of the semiconductor die and the mold compound.

Semiconductor package structure

A system includes a semiconductor die mounted on a packaging substrate, a signal redistribution layer that is formed within the packaging substrate, a power plane that is formed on a surface of the packaging substrate, and a ground plane that is formed within the packaging substrate. The power plane couples the semiconductor die to a capacitor disposed on the packaging substrate and the ground plane is disposed between the power plane and the signal redistribution layer. An advantage of the disclosed system is that loop inductance between power and ground paths to a packaged semiconductor die is reduced, thereby lowering the impedance of the packaged semiconductor die system and signal noise associated with the packaged semiconductor system.

Low-impedance power delivery for a packaged die

A device and method for providing access to a signal of a flip chip semiconductor die. A hole is bored into a semiconductor die to a test probe point. The hole is backfilled with a conductive material, electrically coupling the test probe point to a signal redistribution layer. A conductive bump of the signal redistribution layer is electrically coupled to a conductive contact of a package substrate. An external access point of the package substrate is electrically coupled to the conductive contact, such that signals of the flip chip semiconductor die are accessible for measurement at the external access point.

Method of fabricating a flip chip semiconductor die with internal signal access

Flip chip semiconductor die internal signal access system and method

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Hayward, CA, United States of America

Brian Schieck