Freescale Semiconductor,inc.

Everspin Technologies, Inc.

Intel Corporation

Motorola Corporation

Brian R Butcher

Gregory W Grynkewich

Mark A Durlam

Kenneth H Smith

Kelly Wayne Kyler

Nicholas David Rizzo

Clarence J Tracy

Richard Williams

J Jack Ren

Jaynal Abedin Molla

Mark F Deherrera

Sanjeev Aggarwal

Bradley Neal Engel

John J D'Urso

Thomas Andre

Saied N Tehrani

Phillip G Mather

Frederick B Mancoff

Renu Whig Dave

Jeffrey H Baker

Earl D Fuchs

Thomas V Meixner

Charles A Synder

Srinivas V Pietambaram

Jon Michael Slaughter

Syed M Alam

Kerry Joseph Nagel

Joseph J Nahas

Bradley J Garni

Carlton E Hanna

Steven M Smith

Quan Qi

Anthony Ciancio

Charles W Snyder

Hong Wei Hu

Clarance J Tracy

Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include a die disposed on a first substrate, at least one component adjacent the die on the first substrate, a molding material on the die and the at least one component, wherein the die and the at least one component are completely embedded in the molding material, a second substrate, wherein the first substrate is disposed on a top surface of the second substrate, and at least one communication structure disposed on a surface of the second substrate.

Integrated antenna for direct chip attach connectivity module package structures

A method and memory device is provided for reading data from an ECC word of a plurality of reference bits associated with a plurality of memory device bits and determining if a double bit error in the ECC word exists. The ECC word may be first toggled twice and the reference bits reset upon detecting the double bit error.

MRAM field disturb detection and recovery

A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The process can also include forming a gettering layer having a composition capable of gettering oxygen, and depositing an insulating layer over the gettering layer. The process can further include exposing the insulating layer to a temperature of at least approximately 60&#xb0; C. In one embodiment, after such exposure, a portion of the gettering layer is converted to an insulating material. In another embodiment, an electronic device can include a magnetic tunnel junction and an adjacent insulating layer lying within an opening in another insulating layer.

Electronic device including a magneto-resistive memory device and a process for forming the electronic device

A method of forming a magnetoelectronic device includes forming a dielectric material () surrounding a magnetic bit (), etching the dielectric material () to define an opening () over the magnetic bit () without exposing the magnetic bit (), the opening () having a sidewall, depositing a blanket layer () of cladding material over the dielectric material (), including over the sidewall, removing by a sputtering process the blanket layer () in the bottom of the opening () and the dielectric material () over the magnetic bit (), and forming a conductive material () within the opening () to form a bit line (). This process reduces errors caused by process irregularities such as edges of the bits () protruding and thereby causing defects in the cladding layer () formed thereover. A bit line or digit line so formed may optionally be tapered at the ends () to prevent magnetic reversal of the bit line magnetic moment that otherwise may occur due to external magnetic fields.

Structure and method for fabricating cladded conductive lines in magnetic memories

An apparatus () is provided for sensing physical parameters. The apparatus () comprises a magnetic tunnel junction (MTJ) (), first and second electrodes (), a magnetic field source (MFS) () whose magnetic field () overlaps the MTJ () and a moveable magnetic cladding element () whose proximity (') to the MFS () varies in response to an input to the sensor. The MFS () is located between the cladding element () and the MTJ (). Motion (-) of the cladding element () relative to the MFS () in response to sensor input causes the magnetic field () at the MTJ () to change, thereby changing the electrical properties of the MTJ (). A one-to-one correspondence () between the sensor input and the electrical properties of the MTJ () is obtained.

Sensor having moveable cladding suspended near a magnetic field source

According to an example embodiment, a semiconductor device includes a lower electrode () disposed on an oxide layer (), an upper electrode () disposed on the lower electrode, a dielectric pattern () disposed on the oxide layer and surrounding the upper electrode, the upper electrode protruding above an upper surface of the dielectric pattern, and a contact pattern () that is contiguous with the upper electrode and the dielectric pattern.

Top contact alignment in semiconductor devices

A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.

Methods for contacting conducting layers overlying magnetoelectronic elements of MRAM devices

Methods and apparatus are provided for magnetoresistive memories employing magnetic tunnel junction (MTJ). The apparatus comprises a MTJ (), first () and second () electrodes coupled, respectively, to first () and second () magnetic layers of the MTJ (), first () and second () write conductors magnetically coupled to the MTJ () and spaced apart from the first () and second () electrodes, and at least one etch-stop layer () located between the first write conductor () and the first electrode (), having an etch rate in a reagent for etching the MTJ () and/or the first electrode () that is at most% of the etch rate of the MTJ () and/or first conductor () to the same reagent, so as to allow portions of the MTJ () and first electrode () to be removed without affecting the underlying first write conductor (). In a further embodiment, a second etch-stop layer () is located between the second electrode () and the second write conductor (). Improved yield and performance are obtained.

Magnetic tunnel junction memory and method with etch-stop layer

A method for fabricating a flux concentrating system () for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line () formed in a substrate () and forming a first material layer () overlying the bit line () and the substrate (). Etching is performed to form a trench () in the first material layer () and a cladding layer () is deposited in the trench (). A buffer material layer () is formed overlying the cladding layer () and a portion of the buffer material layer () and a portion of the cladding layer () is removed.

Method for fabricating a flux concentrating system for use in a magnetoelectronics device

Fabricating a magnetoresistive random access memory cell and a structure for a magnetoresistive random access memory cell begins by providing a substrate having a transistor formed therein. A contact element is formed electrically coupled to the transistor and a dielectric material is deposited within an area partially bounded by the contact element. A digit line is formed within the dielectric material, the digit line overlying a portion of the contact element. A conductive layer is formed overlying the digit line and in electrical communication with the contact element.

Magnetoresistive random access memory devices and methods for fabricating the same

A method for fabricating a cladded conductor () for use in a magnetoelectronics device is provided. The method includes providing a substrate () and forming a conductive barrier layer () overlying the substrate (). A dielectric layer () is formed overlying the conductive barrier layer () and a conducting line () is formed within a portion of the dielectric layer (). The dielectric layer () is removed and a flux concentrator () is formed overlying the conducting line ().

Cladded conductor for use in a magnetoelectronics device and method for fabricating the same

Structures for electrical communication with an overlying electrode for a semiconductor element and methods for fabricating such structures are provided. The structure for electrical communication with an overlying electrode comprises a first electrode having a lateral dimension, a semiconductor element overlying the first electrode, and a second electrode overlying the semiconductor element. The second electrode has a lateral dimension that is less than the lateral dimension of the first electrode. A conductive hardmask overlies the second electrode and is in electrical communication with the second electrode. The conductive hardmask has a lateral dimension that is substantially equal to the lateral dimension of the first electrode. A conductive contact element is in electrical communication with the conductive hardmask.

Methods and structures for electrical communication with an overlying electrode for a semiconductor element

Magnetoelectronic device structures and methods for fabricating the same are provided. One method comprises forming a first and a second conductor. The first conductor is electrically coupled to an interconnect stack. A first insulating layer is deposited overlying the first conductor and the second conductor. A via is etched to substantially expose the first conductor. A protective capping layer is deposited by electroless deposition within the via and is electrically coupled to the first conductor. A magnetic memory element layer is formed within the via and overlying the second insulating layer and the second conductor.

Magnetoelectronic devices utilizing protective capping layers and methods of fabricating the same

A method for contacting an electrically conductive electrode overlying a first dielectric material of a structure is provided. The method includes forming a mask layer overlying the electrically conductive electrode and patterning the mask layer to form an exposed electrically conductive electrode material. At least a portion of the exposed electrically conductive electrode material is removed while an electrically conductive veil is formed adjacent the mask layer. A metal contact layer is formed such that said metal contact layer contacts the electrically conductive veil.

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Gilbert, AZ, United States of America

Brian R Butcher