USA As Represented by Secretary of the Navy

Brian R Bennett

John Bradley Boos

Mark B Johnson

James G Champlain

Mario Ancona

Michael P Miller

Walter Kruppa

Theresa F Chick

Nicolas A Papanicolaou

Doewon Park

Richard Magno

Ming-Jey Yang

Paul M Campbell

J Brad Boos

Nicholas A Papanicolou

Brad P Tinkham

Philip R Hammar

An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant intermediate that of the n- and p-channel materials and which is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel and p-channel materials.

Strained InGaAs quantum wells for complementary transistors

A semiconductor device including a heterostructure having at least one low-resistivity p-type GaSb quantum well is provided. The heterostructure includes a layer of InAlAs on an InP substrate, where the InAlAs is lattice matched to InP, followed by an AlAsSbbuffer layer on the InAlAs layer, an AlAsSbspacer layer on the AlAsSbbuffer layer, a GaSb quantum well layer on the AlAsSbspacer layer, an AlAsSbbarrier layer on the GaSb quantum well layer, an InAlSb etch-stop layer on the AlAsSbbarrier layer, and an InAs cap. The semiconductor device is suitable for use in low-power electronic devices such as field-effect transistors.

Low-resistivity p-type GaSb quantum wells

A complementary metal oxide semiconductor (CMOS) device in which a single InGaSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InGaSb layer is part of a heterostructure that includes a Te-delta doped AlGaSb layer above the InGaSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlGaSb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlGaSb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InGaSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.

n- and p-channel field effect transistors with single quantum well for complementary circuits

N- and p-channel field-effect transistors with single quantum well for complementary circuits

This invention pertains to heterojunction bipolar transistors containing a semiconductor substrate, a buffer layer of an antimony-based material deposited on the substrate, a sub-collector layer of an antimony-based material deposited on the buffer layer, a collector layer of an antimony-based material deposited on the sub-collector layer, a base layer of an antimony-based material deposited on the collector layer, an emitter layer of an antimony-based material deposited on the base layer, and a cap layer of an antimony-based material deposited on the emitter layer.

InAlAsSb/InGaSb and InAlPSb/InGaSb heterojunction bipolar transistors

This invention pertains to an electronic device containing a semi-insulating substrate, a buffer layer of an antimony-based material disposed on said substrate, a channel layer of InAsSbmaterial disposed on said buffer layer, a barrier layer of an antimony-based disposed on said channel layer, and a cap layer of InAsSbmaterial disposed on said barrier layer, wherein the device can have frequency of on the order of 500 GHz and a reduced power dissipation.

High electron mobility transistors with Sb-based channels

A modified hybrid Hall effect device is provided which is the combination of a conventional Hall effect device and a second Hall effect device having a Hall plate coupled to a ferromagnetic layer. The hybrid Hall effect device can be used to determine the independent magnetic field vector components comprising a vector magnetic field, such as for determining the x and the z components of a magnetic field, or for measuring the total magnitude of a vector magnetic field of any orientation. The modified Hall Effect device can be adapted for use as a magnetic field sensor for the detection of macroscopic objects that have associated magnetic fields, or for microscopic objects that have been tagged by microscopic magnetic particles. In one specific form, a plurality of hybrid Hall devices are electrically connected together to form an array in which a plurality of rows of hybrid Hall devices are electrically coupled to each other along a current axis, and the array is used for the detection of microscopic objects.

Hybrid Hall vector magnetometer

A modified hybrid Hall effect device is provided which is the combination of a conventional Hall effect device and a second Hall effect device having a Hall plate coupled to a ferromagnetic layer. The hybrid Hall effect device can be used to determine the independent magnetic field vector components comprising a vector magnetic field, such as for determining the {circumflex over (x)} and the {circumflex over (z)} components of a magnetic field, or for measuring the total magnitude of a vector magnetic field of any orientation. The modified Hall Effect device can be adapted for use as a magnetic field sensor for the detection of macroscopic objects that have associated magnetic fields, or for microscopic objects that have been tagged by microscopic magnetic particles. In one specific form, a plurality of hybrid Hall devices are electrically connected together to form an array in which a plurality of rows of hybrid Hall devices are electrically coupled to each other along a current axis, and the array is used for the detection of microscopic objects.

Hybrid hall vector magnetometer

This invention pertains to more sensitive and more stable electronic devices which can sense electrical and magnetic fields. The devices are characterized by InAs channels confined on both sides thereof by a wide band gap AlSb material; protective layers above the AlSb material; modulation doping above the AlSb material; and layers of the InAs channel material containing 1 to 99 mol percent antimony, with the channel material being deposited in the form of alternating monolayers of InSb and InAs, of a ternary mixture of InAsSb.

Modified InAs hall elements

A spin injected diode suitable for nonvolatile memory applications is made of a semiconducting channel capable of carrying current, a single ferromagnetic layer, and a barrier layer between the semiconducting channel and the ferromagnetic layer to protect the integrity of the semiconducting layer and to inhibit interdiffusion of the ferromagnetic material and the semiconductor. During diode readout the output modulation of the diode can be sensed either as the interface resistance between the semiconducting channel and the ferromagnetic layer, or as the output voltage between the semiconducting channel and the ferromagnetic layer when flowing current through the channel and not through the interface. Two of these spin injected diodes can be combined to form a spin injected field effect transistor. This transistor has a first ferromagnetic layer having a first coercivity and a second ferromagnetic layer having a second coercivity smaller than the first coercivity which are spaced apart. A gate is situated between the ferromagnetic layers and includes an insulating layer situated below the gate and between the two ferromagnetic layers. A semiconducting channel layer beneath the first and second ferromagnetic layers and beneath the gate forms a low impedance electrical path between the first and second ferromagnetic layers when a control signal is applied to the gate and a high impedance electrical path between these ferromagnetic layers at all other times. A key component is a barrier layer between the semiconducting channel and the two ferromagnetic layers which performs the same functions as in the diode.

Magnetoresistive spin-injection diode

Heterostructure field-effect transistors (HFETs) and other electronic devs are fabricated from a series of semiconductor layers to have reduced impact ionization. On to a first barrier layer there is added a unique second subchannel layer having high quality transport properties for reducing impact ionization. A third barrier layer having a controlled thickness to permit electrons to tunnel through the layer to the subchannel layer is added as a spacer for the fourth main channel layer. A fifth multilayer composite barrier layer is added which has at least a barrier layer in contact with the fourth channel layer and on top a sixth cap layer is applied. The device is completed by adding two ohmic contacts in a spaced apart relationship on the sixth cap layer with a Schottky gate between them which is formed in contact with the fifth barrier layer. The second subchannel layer and the fourth main channel layers are made of materials which have the proper respective energy gaps and ground state energies such that during use the transfer of hot electrons from the main channel into the subchannel is made probable to reduce impact ionization in the main channel. In the preferred AlSb/InAs-based HFETs, the use of an Is InAs subchannel layer under the main InAs channel improves the performance of the HEMTs particularly for gate lengths in the deep-submicron regime. The devices exhibit higher transconductance, lower output conductance, reduced gate leakage current, higher operating drain voltage, and improved frequency performance.

Channel design to reduce impact ionization in heterostructure

An electronic device characterized by a GaAs substrate and a base disposed n the substrate, the base comprising InAs channel layer, AlSb layer above the channel layer, In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y layer containing at least In, Al, and As disposed above the AlSb channel layer, InAs cap layer disposed above and in contact with the In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y layer disposed below the InAs channel layer and in contact with the substrate, p.sup.+ GaSb layer disposed within the AlSb layer, Schottky gate with a pad disposed on and in contact with the In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y layer, at least one ohmic contact disposed on the InAs cap layer, and a trench extending through the base to the substrate isolating the gate bonding pad from the device and providing a gate air bridge which prevents contact between the gate and the InAs layer. The gate air bridge fabrication is accomplished by a liquid etchant containing more than half, on volume basis, of concentrated lactic acid or acetic acid with remainder hydrogen peroxide and concentrated hydrofluoric acid. The etchant attacks InAs, In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y, AlSb, and GaSb but does not attack GaAs and Au-based alloys.

Growing community of inventors

Arlington, VA, United States of America

Brian R Bennett