Credence Systems Corporation

Formfactor, Inc.

Brian J Arkin

Garry C Gillette

David Scott

John Mark Oonk

Alistair Nicholas Sporck

Gary L Schaps

David Chan

Ha Nguyen

A probe card assembly can include a plurality of probes disposed on a substrate and arranged to contact terminals of a semiconductor wafer. Switches can be disposed on the probe card assembly and provide for selective connection and disconnection of the probes from electrical interconnections on the probe card assembly.

Wafer level contactor

A technique for distributing power to a plurality of dies uses a probe card. The probe card can include a plurality of regulators, each regulator accepting a bulk power input and producing a regulated output. The regulated output can be controlled by a programmable controller that accepts a tester-controlled power input and adjusts the regulated outputs as a function of the tester-controlled power input.

Method and apparatus for enhanced probe card architecture

An integrated circuit tester for testing an IC device under test (DUT) during a succession of test cycles includes a pattern generator programmed to generate data before each test cycle encoded to specify all test activities to be carried out during the test cycle and to specify for each test activity a time during the test cycle at which the test activity is to be carried out and a DUT IO pin at which the test activity is to be carried out. Multiple programmable tester channels each comprise multiple DUT interface circuits, each of which can be connected to a separate DUT IO pin for carrying out test activities at that DUT IO pin when signaled to do so, and hardware resources programmed by decoding instructions to decode the data from the pattern generator for each test cycle and initiate each specified test activity by signaling the DUT interface circuit that is specified for the test activity at the time specified for the test activity.

Integrated circuit tester with software-scaleable channels

An algorithmic pattern generator for generating an output vector on each pulse of a clock signal includes a vector memory for storing a vector and an accompanying repeat number at each of several addresses. On each of N consecutive clock signal pulses, a repeat processor appends an instance of a vector read out of the vector memory to the pattern generator's output vector sequence. An instruction processor causes the instruction memory to read out instructions and responds to each instruction by telling the instruction processor to signal the address counter to supply the starting address to the vector memory and to thereafter periodically increment the starting address for M consecutive clock signal cycles. When appending N instances of each vector to the pattern generator output sequence, the repeat processor inhibits the address counter from incrementing its output address for N&minus;1 cock signal cycles.

High-speed algorithmic pattern generator

An integrated circuit (IC) tester employs a pattern generator including an instruction processor executing an algorithmic program stored in a program memory. The program defines a sequence of vectors defining test activities to be carried out during successive cycles of a test on an IC. In the course of executing the program, the instruction processor stores in various registers and counters &ldquo;program status&rdquo; data that the processor uses to keep track of program execution. The status data may include, for example, the current program memory address, loop and repeat counts, return addresses and the like. The pattern generator also includes a random access &ldquo;program status&rdquo; memory for storing a selected portion of the program status data at selected points during a test. The algorithmic program defining the vectors to be produced for each cycle of the test also selects a test event (such as a DUT failure) that is to trigger program status data storage during any test cycle, selects the particular status data to be stored in response to the test event, and selects the status memory address at which the data is to be stored. Test analysis software may read the program status data out of the program status memory following the test and use it to determine the status of program execution at the time the triggering events occurred.

Integrated circuit tester having a program status memory

A memory tester tests a random access memory device under test (DUT) comprising addressable rows and columns of memory cells, and provides a host computer with enough information to determine how to efficiently allocate spare rows and columns for replacing rows and columns containing defective memory cells. During a test the memory tester writes a bit into each address of an error capture memory (ECM) to indicate whether a correspondingly addressed memory cell of the DUT is defective. The tester also counts of the number of memory cells of each row and column that are defective. After the test the counts are supplied to the host computer. When the host computer is unable to determine how to allocate the spare rows and columns from the counts alone, it requests the tester to process the data in the ECM to determine and supply the host computer with addresses of the defective memory cells.

Apparatus for testing memories with redundant storage elements

A parallel processing pattern generation system for an integrated circuit tester includes two pattern memories, a main pattern generator, and two auxiliary pattern generators. Each pattern memory may receive and store data patterns from a host computer before the test. All three pattern generators may produce data pattern sequences in a variety of ways by executing separately stored algorithmic programs. The pattern sequences generated by each of the two auxiliary pattern generators separately address the two pattern memories so that either one or both of the two pattern memories may read out pattern data during a test. The main pattern generator includes a routing circuit for receiving as inputs a portion of the pattern data generated by the main pattern generator itself and the pattern data read out of the two pattern memories. The routing circuit, controlled by another portion of the pattern data produced by the main pattern generator, selects from among its inputs on a bit-by-bit, cycle-by-cycle basis to provide pattern data for controlling tester activities during each cycle of a test.

Parallel processing pattern generation system for an integrated circuit

Each channel of an integrated circuit tester includes at least one timing signal generator for producing an output timing signal for triggering various types of test events carried out by the tester channel. At the start of each cycle of a test, each timing signal generator receivies input timing data referencing a time at which a test event is to occur and also receives input format data indicating the format of that test event. Each timing signal generator then generates its output timing signal before the event time referenced by the timing data with a lead time selected by the input format data. Each timing signal generator may be independently calibrated such that the format data always selects the appropriate lead time for the event to be triggered so that each type of event occurs at the time indicated by the input timing data regardless of the nature of the event being triggered.

Format sensitive timing calibration for an integrated circuit tester

A modular integrated circuit tester includes a set of tester modules for carrying out a sequence of tests on an integrated circuit device under test (DUT). Each module includes a memory for storing instruction sets indicating how the module is to be configured for each test of the sequence. Before the start of each test, a microcontroller in each module executes an instruction set to appropriately configure the module for the test. The microcontroller in each module thereafter sends a ready signal to a start logic circuit in each other module indicating that it is ready to perform the test. When the microcontrollers of all modules taking part in the test have signaled they are ready, the start logic circuit in each module signals its microcontroller to begin the test. The modules then carry out the test with their activities synchronized to a master clock signal. The process of configuring the modules, generating the ready signals and commencing a test is repeated for each test of the sequence.

Modular integrated circuit tester with distributed synchronization and

A programmable delay circuit produces an OUTPUT signal following an INPUT signal with a delay selected by input delay selection data. The delay circuit includes a tapped delay line, a multiplexer, a delay adjustment stage and a programmable encoder. The delay line includes a set of N delay elements connected in series for successively delaying the INPUT signal to produce a set of N output TAP signals. The multiplexer passes a selected TAP signal to the delay adjustment stage. The delay adjustment stage delays the selected TAP signal to produce the OUTPUT signal. The programmable encoder encodes the input delay selection data to provide signals for controlling the multiplexer and for adjusting the delay of the delay adjustment stage. The manner in which the encoder encodes each separate delay selection data value is adjustable so that each of the N selectable delays can be separately calibrated.

Programmable delay circuit having calibratable delays

An integrated circuit tester includes a host computer, a pattern generator and a set of tester circuits. The tester circuits perform test activities on an integrated circuit in response to sequences of test control data arriving via a set of data lines. The host computer may write parameter control data into the tester circuits via a bus telling the tester circuits how to adjust various parameters of test activities to be performed in response to a next arriving sequence of test control data. The host computer is also linked to the pattern generator via that same bus and writes pattern control data into the pattern generator via the bus. The pattern control data tells the pattern generator to generate alternating sequences of test control data and pattern control data. As it is generated, each test control data sequence is delivered to the tester circuits via the data lines to tell the tester circuits how to carry out a sequence of test activities. As each parameter control data sequence is generated, the parameter control data is written into the tester circuits via the bus to set the test parameters for a next sequence of test activities to be performed. Thus once programmed with pattern control data from the host, the pattern generator can cause the tester circuits to carry out a sequence of tests and to appropriately adjust their test parameters before each test without further assistance from the host computer.

Integrated circuit tester having pattern generator controlled data bus

A delay line formed by a set of series-connected logic gates produces a sequence of output pulses in delayed response to a sequence of input pulses. The delay provided by a delay line changes with the frequency of its input pulse sequence because of temperature change in the gates due to changing power usage. Therefore a pulse stuffing circuit is provided to monitor the sequence of input pulses supplied to the delay line and to generate one or more stuff pulses when a period between successive input pulses exceeds a target maximum period. Each stuff pulse is sent as an additional input pulse to the delay circuit to decrease the period between input signal pulses. Although the delay circuit adds extra pulses to its output pulse sequence in response to the stuff pulses, the pulse stuffing circuit includes a gating circuit for removing those extra pulses from the output pulse sequence.

Pulse stuffing circuit for programmable delay line

A formatter circuit for channel of a multiple channel integrated circuit tester includes a drive control circuit, a compare circuit, and a random access memory (RAM). The RAM converts each value of input format selection data to corresponding format control data supplied to the drive control and compare circuits. The drive control circuit generates a set of drive control signals which determine the state of a test signal the tester channel supplies to a terminal of a device under test (DUT). The compare circuit determines whether a DUT output signal at the terminal is of an expected logic state. The drive and compare circuits employ multiplexers controlled by the format control data output of the RAM to select from among a variety of alternative data sources referencing desired states of the drive control signals or expected states of the DUT output signals. The formatter architecture permits flexible use of input reference data to provide a wide variety of selectable drive and compare formats.

Programmable formatter circuit for integrated circuit tester

An integrated circuit tester includes a pattern generator, a main and an auxiliary period generator, and set of tester channels, one for each terminal of an integrated circuit device under test (DUT). A test is organized into a succession of main test cycles, each divided into two or more auxiliary test cycles. The main period generator indicates the start of each main test cycle and the auxiliary period generator indicates the start of each auxiliary test cycle. Each tester channel is programmed to respond either to the main period generator or to the auxiliary period generator. At the start of each main test cycle, the pattern generator supplies data to each tester channel indicating a test activity to be carried out at the DUT terminal and indicated a time relative to a start of a test cycle at which the activity is to be carried out. Each tester channel programmed to respond to the main period generator carries out the indicated test activity once at the indicated time during the main test cycle. Each tester channel programmed to respond to the auxiliary period generator repeats the indicated test activity at the indicated time during each successive auxiliary test cycle spanned by the main test cycle.

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Pleasanton, CA, United States of America

Brian J Arkin