Cadence Design Systems, Inc.

Brian Edward Foutz

Vivek Chickermane

Krishna Chakravadhanula

Christos Papameletis

Paul Alexander Cunningham

Steev Wilcox

Patrick Gallagher

Sarthak Singhal

Puneet Kumar Arora

Dale Meehl

Subhasish Mukherjee

Louis Christopher Milano

David George Scott

Prateek Kumar Rai

Nitin Parimi

Norman Robert Card

Sandeep Bhatia

Sameer Chakravarthy Chillarige

Ankit Bandejia

Bharath Nandakumar

Carl Barnhart

A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that divide the test-point nodes into a plurality of test-point sharing groups in which each of the test-point nodes is associated with one of the clock-gates that is common to each of at least one flip-flop of the portion of the functional logic coupled to each of the respective test-point nodes in the test-point sharing group. The test-point flop allocation module can further allocate one of the test-point flops to each of the test-point sharing groups. The EDA application also includes a circuit layout module configured to generate a circuit layout associated with the circuit design based on the circuit netlist. The circuit layout is employable to fabricate an IC chip.

Clock-based test-point flop sharing in a circuit design

An integrated circuit (IC) chip includes an intellectual property (IP) core that executes logical operations to perform a function. The IC chip also includes a scan chain array for testing the IP core, and a pseudo random pattern generator (PRPG) that provides a pseudo random pattern based on a seed. The IC chip includes a spreader network that applies a first pseudo random code to a first edge of a die of the IC chip and a second pseudo random code to a second edge of the die of the IC chip in response to the pseudo random pattern and combines the first and second code to form a 2D code that is applied to the scan chain array. A security signature register of the IC chip outputs a signature corresponding to a response from the scan chain array that is employable to detect changes to an IC design.

IC chip with IC design modification detection

Embodiments included herein are directed towards a launch off shift circuit module. Embodiments included a first flip-flop configured to receive a clock signal and a scan enable signal. Embodiments may further include a combinational logic circuit configured to receive an input from the first flip-flop and a launch off shift mode signal. The first flip-flop and the combinational logic circuit may be located inside a launch off shift module boundary.

Launch off shift process

This disclosure relates scan chain stitching. In one example, scan chain elements from a scan chain element space can be received for a scan chain partition. The scan chain elements can be grouped based on scan chain element grouping criteria to form scan chain groups. Scan chain data identifying a number of scan chains for the scan chain partition can be received. The scan chains can be scan chain balanced across the scan chain groups to assign each scan chain to one of the scan chain groups. The scan chain elements associated with each scan chain of the scan chains can be scan chain element balanced. Scan chain elements for each associated scan chain can be connected to form a scan chain data test path during a generation of scan chain circuitry in response to the scan chain element balancing.

Systems and methods for scan chain stitching

A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that is configured to evaluate the circuit netlist to determine compatibility of the test-point nodes in the circuit netlist. The test-point flop allocation module can further allocate each of the test-point flops to a test-point sharing group comprising a plurality of compatible test-point nodes. The EDA application also includes a circuit layout module configured to generate a circuit layout associated with the circuit design, the circuit layout comprising the functional logic and scan-chains comprising the test-point flops allocated to the test-point sharing groups in response to the circuit netlist. The circuit layout is employable to fabricate an integrated circuit (IC) chip.

Test-point flop sharing with improved testability in a circuit design

Methods and design system for generating 2-dimensional distribution architecture for testing integrated circuit design that utilizes double grid to minimize interdependencies between grid cells and the associated functional logic to facilitate the a physically efficient scan of integrated circuit designs, that simultaneously minimizes required test application time ('TAT'), test data volume, tester memory and cost associated with design for test ('DFT'), while also retaining test coverage. An additional grid parallel to a 2-dimensional XOR grid may be implemented that improves the quality of test coverage by optimally adding additional data inputs which decreases correlations between grid cells. A column spreader may feed data into column wires and row spreader may feed data into column wires. The double grid allows data to be fed into two wires, row and column, respectively, which provides twice as much stimulus data in each direction, without significantly increasing the wiring used to build the grid.

Method to improve testability using 2-dimensional exclusive or (XOR) grids

Exemplary embodiments of the present disclosure relate to a clock distribution network for a scan design, which may include, for example, a clock signal network(s), and a plurality of partitioned clock signal networks coupled to the clock signal network(s) through a controlling logic(s); where the controlling logic(s) may be configured to stagger a clock signal from the clock signal network(s), and where each of the partitioned clock signal networks may be connected to a group of flip-flops. A first partitioned clock signal network of the partitioned clock signal networks may be connected to a first group of flip-flops and a second partitioned clock signal network of the partitioned clock signal networks may be connected to a second group of flip-flops, and where the first group of flip-flops may be different than the second group of flip-flops. The controlling logic(s) may include a shift register(s).

Low-power shift with clock staggering

Methods and computer-readable media for testing integrated circuit designs implement a physically efficient scan by optimally balancing and connecting scan segments in a 2-dimensional compression chain architecture. A compression architecture that provides an optimal and balanced configuration of scan segments in 2D compression grids to not only decrease test time, but also to maximize compression efficiency and limit wiring congestion for IC designs that contain complex scan segments facilitates efficient scanning of data by bisecting the elements into balanced partitions of the same target scan length. A segment padding algorithm, followed by a bisecting algorithm and ultimately an element swapping algorithm may be applied to optimally balance and connect scan segments in 2-D compression chains, optimizing an efficient compression architecture which minimizes scan testing resources and time.

Method for optimally connecting scan segments in two-dimensional compression chains

Systems and methods disclosed herein provide for an integrated circuit partitioned into a plurality of regions of a two-dimensional grid, wherein each region of the grid corresponds to similarly located scan flops. The systems and methods also provide for enabling clock gates to scan flops in some regions of the integrated circuit and disabling clock gates to other regions in order to better manage power dissipation during ATPG. Specifically, toggle disabling templates are applied during ATPG in order to enable clock gates in certain regions of the two-dimensional grid.

2D compression-based low power ATPG

Systems disclosed herein provide for efficient top-level compactors for systems on a chip (SoCs) with multiple identical cores. Embodiments of the systems provide for compactors with a time-skewed assignment configuration, compactors with a space-skewed assignment configuration, compactors with time/space-skewed assignment configuration, and compactors that can selectively switch between the time/space-skewed assignment configuration and a symmetric assignment configuration.

SoC top-level XOR compactor design to efficiently test and diagnose multiple identical cores

Systems and methods for a sequential decompressor which builds equations predictably provide a first-in, first out ('FIFO') shift register which is fed by a first XOR decompressor and provides outputs to a second XOR decompressor.

Method and system for construction of a highly efficient and predictable sequential test decompression logic

Systems and methods efficiently bring additional variables into a Pseudo-Random Pattern Generator ('PRPG') in the early cycles of an automatic test pattern generation ('ATPG') process without utilizing any additional hardware or control pins. Overscanning (e.g., scanning longer than the length of the longest channel) for some additional cycles brings in enough variables into the PRPG. Data corresponding to earlier cycles of the ATPG process is removed.

Method and system for improving efficiency of sequential test compression using overscan

Systems and methods disclosed herein provide for generating extra variables for an ATPG system utilizing compressed test patterns in the event an ATPG process is presented with faults requiring a higher number of care-bits than can be supported efficiently by the current hardware. The systems and methods provide for a multi-stage decompressor network system with an embedded serializer-deserializer. The systems and methods use a XOR decompressor in a first stage and a serializer-deserializer in conjunction with a second XOR decompressor in a second stage.

Method and system for improving efficiency of XOR-based test compression using an embedded serializer-deserializer

Methods and apparatus for decompressing test data using XOR trees for application to scan chains of a design for test (DFT) integrated circuit in a physically efficient construction are disclosed. Moreover, methods and apparatus for compressing test response data from scan chains in a DFT integrated circuit in a physically efficient construction are disclosed. The XOR tree decompression method may comprise splitting signals at each node of the XOR trees according to distribution logic implemented by a set of XOR gates. The XOR tree compression method may comprise combining signals at each node of the XOR trees according to combination logic implemented by a set of XOR gates.

Method for using XOR trees for physically efficient scan compression and decompression logic

Systems and methods disclosed herein provide for utilizing extra variables in the decompression equation set of an ATPG process for test patterns requiring an excess number of care bits than can be supported efficiently by the current hardware. An elastic interface is utilized between a tester and a decompressor network (e.g., sequential and combinational decompressors) in order to expand the test pattern length and/or the number of input variables. The systems and methods also provide care bits in early scan cycles of the ATPG process for sequential decompressors starting from a fixed state.

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Charlottesville, VA, United States of America

Brian Edward Foutz