Intel Corporation

Silicon Genesis Corporation

Brian E Roberds

Brian S Doyle

Robert S Chau

Anand S Murthy

Sharon N Farrens

Jack T Kavalieros

Mark L Doczy

Rafael Rios

Reza Arghavani

Jin Hyung Lee

Doulgas W Barlage

Peng Cheng

Quat T Vu

Chunlin Liang

Sandy S Lee

Cindy Colinge

A method for fabricating a strained silicon film to a silicon on insulation (SOI) wafer. A layer of oxide is deposited onto a wafer that has a stack structure of a first base substrate, a layer of relaxed film and a second layer of strained film. The SOI wafer has a stack structure of a second base substrate and a layer of oxidized film. The SOI wafer is attached to the wafer and is heated at a first temperature. This causes a silicon dioxide (SiO) dangling bond to form on the second base substrate of the SOI wafer, transferring the strained film from one wafer to the other.

Creation of high mobility channels in thin-body SOI devices

A method for fabricating a strained silicon film to a silicon on insulation (SOI) wafer. A layer of oxide is deposited onto a wafer that has a stack structure of a first base substrate, a layer of relaxed film=and a second layer of strained film. The SOI wafer has a stack structure of a second base substrate and a layer of oxidized film. The SOI wafer is attached to the wafer and is heated at a first temperature. This causes a silicon dioxide (SiO) dangling bond to form on the second base substrate of the SOI wafer, transferring the strained film from one wafer to the other.

A method for fabricating a strained silicon film to a silicon on insulation (SOI) wafer. A layer of oxide is deposited onto a wafer that has a stack structure of a first base substrate, a layer of relaxed film-and a second layer of strained film. The SOI wafer has a stack structure of a second base substrate and a layer of oxidized film. The SOI wafer is attached to the wafer and is heated at a first temperature. This causes a silicon dioxide (SiO) dangling bond to form on the second base substrate of the SOI wafer, transferring the strained film from one wafer to the other.

A novel transistor structure and its method of fabrication. According to the present invention, the transistor includes an intrinsic silicon body having a first surface. A gate dielectric is formed on the first surface of the intrinsic silicon body. A gate electrode is formed on the gate dielectric wherein the gate electrode comprises a mid-gap work function film on the gate dielectric. A pair of source/drain regions are formed on opposite sides of the intrinsic silicon body.

Transistor structure and method of fabrication

A method for chemically bonding semiconductor wafers and other materials to one another without exposing wafers to wet environments, and a bonding chamber for in situ plasma bonding are disclosed. The in situ plasma bonding chamber allows plasma activation and bonding to occur without disruption of the vacuum level. This precludes rinsing of the surfaces after placement in the chamber, but allows for variations in ultimate pressure, plasma gas species, and backfill gases. The resulting bonded materials are free from macroscopic and microscopic voids. The initial bond is much stronger than conventional bonding techniques, thereby allowing for rougher materials to be bonded to one another. This bonded materials can be used for bond and etchback silicon on insulator, high voltage and current devices, radiation resistant devices, micromachined sensors and actuators, and hybrid semiconductor applications. This technique is not limited to semiconductors. Any material with sufficiently smooth surfaces that can withstand the vacuum and plasma environments may be bonded in this fashion.

In situ plasma wafer bonding method

The invention relates to a transistor that includes a semiconductive layer on an insulator layer. Below the insulator layer is a substrate and a contact is disposed in the insulator layer that originates at the substrate and terminates in the insulator layer. The contact is aligned below the transistor junction. The invention also relates to a process flow that is used to fabricate the transistor. The process flow includes forming the contact by either a spacer etch or a directional, angular etch.

Silicon-on-insulator structure and method of reducing backside drain-induced barrier lowering

A method for forming a strain layer on an underside of a channel in an MOS transistor in order to produce a mechanical stress in the channel, increasing a mobility of carriers in the channel and an apparatus produced from such a method.

Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel

Method of fabricating a semiconductor device. The semiconductor device comprises a substrate, a high-k gate dielectric layer formed on the substrate, and a hydrogen-free gate electrode deposited on the high-k gate dielectric layer wherein the hydrogen-free gate electrode is conductive. The method comprises depositing the high-k gate dielectric layer on the substrate, sputtering the gate electrode on the gate dielectric layer and treating the gate electrode such that the gate electrode is conductive.

Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication

A transistor using mechanical stress to alter carrier mobility. Voids are formed in one or more of the source, drain, channel or gate regions to introduce tensile or compressive stress to improve short channel effects.

MOS transistor using mechanical stress to control short channel effects

A method for fabricating a strained silicon film to a silicon on insulation (SOI) wafer. A layer of oxide is deposited onto a wafer that has a stack structure of a first base substrate, a layer of relaxed film and a second layer of strained film. The SOI wafer has a stack structure of a second base substrate and a layer of oxidized film. The SOI wafer is attached to the wafer and is heated at a first temperature. This causes a silicon dioxide (SiO ) dangling bond to form on the second base substrate of the SOI wafer, transferring the strained film from one wafer to the other.

A method of decreasing the dielectric constant of a dielectric layer. First, a dielectric layer is formed on a first conductive layer. A substance is then implanted into the dielectric layer.

Method for reduced capacitance interconnect system using gaseous implants into the ILD

A method for chemically bonding semiconductor wafers and other materials to one another without exposing wafers to wet environments, and a bonding chamber for in situ plasma bonding are disclosed. The in situ plasma bonding chamber allows plasma activation and bonding to occur without disruption of the vacuum level. This precludes rinsing of the surfaces after placement in the chamber, but allows for variations in ultimate pressure, plasma gas species, and backfill gases. The resulting bonded materials are free from macroscopic and microscopic voids. The initial bond is much stronger than conventional bonding techniques, thereby allowing for rougher materials to be bonded to one another. These bonded materials can be used for bond and etchback silicon on insulator, high voltage and current devices, radiation resistant devices, micromachined sensors and actuators, and hybrid semiconductor applications. This technique is not limited to semiconductors. Any material with sufficiently smooth surfaces that can withstand the vacuum and plasma environments may be bonded in this fashion.

The invention relates to a semiconductor structure that is formed by delaminating a semiconductor substrate and by bonding the top section of the substrate to a transfer substrate. Delaminating is carried out by causing a polymer film to achieve greater adhesion that an embrittlement layer in the semiconductor substrate.

Growing community of inventors

Escondido, CA, United States of America

Brian E Roberds