Freescale Semiconductor,inc.

Other

Motorola Corporation

Cadence Design Systems, Inc.

Brett W Murdock

William C Moyer

Michael D Fitzsimmons

Craig D Shaw

Robert N Ehrlich

Jeremy A Jacobson

Jeffrey William Scott

William Paul Alberth, Jr

Scott A Steele

Jimmy Gumulja

Matthew D Akers

Benjamin C Eckermann

A system and method in accordance with the present invention provides for a solution benefiting from providing for non-duplicative access to data located in a system memory via the alignment of transaction sub-command breaking points with memory burst boundaries associated with the system memory, by creating a plurality of sub-commands for a transaction each having breaking points, identifying a plurality of memory burst boundaries for the system memory each having burst boundary points, and aligning a plurality of breaking points with a plurality of burst boundary points to provide single access to data located in the system memory.

Method and system for aligning transaction split boundaries to memory burst boundaries

A method includes receiving, at an interconnect, a first transaction request from a first requesting module. The first transaction request includes a request to utilize at least one system resource accessible via the interconnect. The method further includes determining potential interferences at the interconnect expected to occur as a result of a utilization of the at least one system resource by the first requesting module and initiating processing of the first transaction request at the interconnect. The method additionally includes authorizing processing of a second transaction request from a second requesting module during the processing of the first transaction request based on the determined potential interferences.

Selective transaction request processing at an interconnect during a lockout

A flexible interrupt controller circuit and methodology are provided which use an interrupt circuit () that multiplexes () a plurality of interrupt priority registers () based on the current context of the system that is identified in mode control selector (). By using the mode control selector () to selectively couple different priority level assignments to a priority encoding module (), context sensitive switching of the priority levels assigned to each interrupt request can be implemented with reduced latency. The context switch could be based on an OS context ID, power management modes, security modes, and other system defined modes where priority levels would differ. The selected priority level information is used to provide an interrupt request signal () which will cause an interrupt to occur in the data processing system.

Hardware managed context sensitive interrupt priority level control

A data processing system may comprise an initiator device having an output whose timing is referenced by a clock input alone corresponding to a first delay along a signaling path. The exemplary data processing system further may further comprise a target device having an input whose timing is referenced by a clock input alone corresponding to a second delay along the signaling path and a system bus interconnected between the initiator device and the target device within the signaling path. The exemplary data processing system may further comprise a dynamic timing bridge coupled to the system bus within the signaling path, wherein responsive to a control signal representative of at least one system characteristic, the dynamic timing bridge performs one selected from the group consisting of (i) inserting a cyclic latency within the signaling path and (ii) not inserting the cyclic latency within the signaling path.

Bus having a dynamic timing bridge

A method is disclosed whereby a priority amongst transactions capable of being processed at a common time is determined based upon a transaction identifier associated with each of the transaction. The transaction identifier can either directly indicate a priority amongst the transactions, or use to index storage locations that indicate priority values. The transaction identifiers can be selected to be associated with a transaction by the requesting device or other priority determination module based upon predefined criteria.

Method of accessing information and system therefor

A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is being accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.

Data processing system with bus access retraction

A crossbar switch () arbitrates for access from multiple bus masters (and) to multiple addressed slave ports (and) that have overlapping address ranges. In one form, the address ranges are the same address range. The crossbar switch () uses shared slave port control circuitry (), configuration registers () and slave port arbiter logic (and) to arbitrate for access when all the addressed ports are busy. A determination is made as to whether new access requests are higher or lower in priority than existing accesses. A determination on where to direct a new access request is made based upon a prediction of which of certain multiple accesses will complete first based on various factors including the number of data beats requested as well as wait state information. In one mode, the wait state information is determined dynamically.

Method of accessing memory via multiple slave ports

Embodiments of the present inventions relate to processors having sequential address indicator signals, also referred to as sequence signals, for indicating when accessed addresses are sequential. One embodiment relates to a processing system for accessing memory having an address bus for providing a current address and a previous address to memory, a data bus, an execution unit, and a decode control unit. The processing system further includes a fetch unit, coupled to the execution unit, the decode control unit, the address bus, and the data bus, for generating a first sequence signal that when negated indicates that the current address may not be sequential to the previous address, a second sequence signal that when negated indicates that the current address is not sequential to the previous address, and a third sequence signal that when negated indicates that the current address, if it is an instruction address, is not sequential to the previous address that was an instruction address.

Processing system having sequential address indicator signals

A system () having a plurality of bus masters () coupled to an arbiter () is disclosed. An arbiter () is coupled to a first storage location () and a second storage location (), where the first and second storage locations store bus master parking information for a system bus (). The arbiter () receives a parking context indicator () that is used to select one of the first and second storage locations () to provide bus master parking information to the arbiter ().

Method and system of bus master arbitration

A system for accessing memory devices includes a processing module coupled to a set of outputs and memory operably coupled to the processing module. The memory stores operational instructions that cause the processing module to perform a plurality of operations. A first one of the plurality of operations includes utilizing a first output to provide a first data lane enable to facilitate accessing of a portion of a first memory storage location associated with a first memory address when in a first mode of operation. A second one of the plurality of operations includes utilizing the first output to provide an address bit of a second memory address to facilitate designation of a second memory storage location when in a second mode of operation.

Method and system for accessing memory devices

An arbitration control circuit () for arbitrating access to a slave device () by a plurality of master devices () includes an undefined length burst (ULB) arbitration logic circuit (). The ULB arbitration logic circuit () includes a counter () and a control register (). The control register () stores a predetermined value. During a ULB access of the slave device (), the counter () is loaded with the predetermined value and is decremented for each beat of the undefined length burst access. Arbitration of the slave device (4) is only allowed after the predetermined number of access beats during the undefined length burst access.

Arbiter having programmable arbitration points for undefined length burst accesses and method

Crossbar switch that supports a multi-port slave device and method of operation

A system and method of communications usage management for multiple networked devices such as cellular telephones in a telecommunications network. A management database is provided for storing communications attributes for at least one networked device. The stored communications usage attributes serve as criteria for regulating access of the networked devices to the system. The users of the devices may purchase a quantity of transferable units, such as usage minutes over the system network, with the units being redeemable for goods and/or services on the system, thus facilitating transfer of units between users. A user interface is provided as a system management device for accessing the management database to configure the communications usage attributes for defining the transfer and usage criteria. Communications usage software operable with the network devices computes usage times to provide an accounting of usage and regulation in accordance with the management database. In the described embodiment, short message service (SMS) traffic is used for messages between networked devices used by several users to purchase quantities of redeemable units for exchange, commercial activities, or recreation which may be facilitated through the system operator.

Growing community of inventors

Austin, TX, United States of America

Brett W Murdock