International Business Machines Corporation

Globalfoundries Inc.

Infineon Technologies Ag

Stmicroelectronics Gmbh

Other

Samsung Electronics Co., Ltd.

Brett H Engel

Keith Kwong Hon Wong

Vincent James McGahay

Domingo A Ferrer

Arun Vijayakumar

Soon-Cheon Seo

Terence Lawrence Kane

Diana Llera-Hurlburt

Anthony K Stamper

Yun Yu Wang

Timothy Joseph Dalton

John Anthony Fitzsimmons

Tze-Chiang Chen

Yun-Yu Wang

Erdem Kaltalioglu

Hormazdyar M Dalal

Hazara Singh Rathore

Ying Li

Eric Gerhard Liniger

Du Binh Nguyen

Birendra N Agarwala

Ann H McDonald

Chunyan E Tian

Naftall E Lustig

Richard W Procter

Kevin Shawn Petrarca

Richard Stephan Wise

Sandra Guy Malhotra

Richard Paul Volant

Thomas M Shaw

Chandrasekhar Narayan

Kwong Hon Wong

Viraj Yashawant Sardesai

Ju Youn Kim

Ian D Melville

Lindsey H Hall

William Francis Landers

Pietro Montanini

Steven R Soss

Kelly Malone

John A Miller

Mark Hoinkis

Randolph F Knarr

Habib Hichri

Charles Robert Davis

Henry Atkinson Nye, Iii

Patrick William Dehaven

Richard Stephen Wise

Ronald Dean Goldblatt

Scott W Crowder

Jeffrey R Marino

Jin Zheng Wallner

John D Sylvestri

David F Hilscher

Roderick Miller

Bernd E Kastenmeier

Brian Wayne Herbst

Chung-Ping Eng

Stephen M Lucarini

Arthur W Martin

John Charles Petrus

Sanjit Kumar Das

Barry Jack Ginsberg

Gerald Leake, Jr

André P Labonté

Dermott A Macpherson

A method of forming a titanium nitride (TiN) diffusion barrier includes exposing a deposition surface to a first pulse of a titanium-containing precursor and to a first pulse of a nitrogen-rich plasma to form a first TiN layer with a first nitrogen concentration making a lower portion of the TiN diffusion barrier, the first nitrogen concentration of the first TiN layer is increased by the first pulse of the nitrogen-rich plasma reducing a reactivity of the lower portion of the TiN diffusion barrier to prevent fluorine diffusion. The first TiN layer is exposed to second pulses of the titanium-containing precursor and the nitrogen-rich plasma to form a second TiN layer with a second nitrogen concentration above the first TiN layer making an upper portion of the TiN diffusion barrier, the first pulse of the nitrogen-rich plasma has a substantially longer duration than the second pulse of the nitrogen-rich plasma.

Diffusion barrier layer formation

A method includes forming a first metal liner conformally along a sidewall and a bottom of a contact opening. A second metal liner is formed above and in direct contact with the first metal liner, a grain size of the first metal liner is larger than a grain size of the second metal liner. A barrier layer is formed above and in direct contact with the second metal liner and the contact opening is filled with a conductive material to form a middle-of-the-line contact.

Automatic capacitance tuning for robust middle of the line contact and silicide applications

Use of a replacement metal gate (RMG) process provides an opportunity to create precision polysilicon resistors alongside metal gate transistors. During formation of a sacrificial polysilicon gate, the precision polysilicon resistor can also be formed from the same polysilicon film. The polysilicon resistor can be slightly recessed so that a protective insulating layer can cover the resistor during subsequent replacement of the sacrificial gate with a metal gate. The final structure of the precision polysilicon resistor fabricated using such a process is more compact and less complex than existing structures that provide metal resistors for integrated circuits having metal gate transistors. Furthermore, the precision polysilicon resistor can be freely tuned to have a desired sheet resistance by either implanting the polysilicon film with dopants, adjusting the polysilicon film thickness, or both.

Precision polysilicon resistors

A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.

Overlapping contacts for semiconductor device

An integrated circuit having a mis-alignment tolerant electrical contact is formed by providing a semiconductor containing substrate over which is a first FET gate laterally bounded by a first dielectric region, replacing an upper portion of the first FET gate with a second dielectric region, applying a mask having an opening extending partly over an adjacent source or drain contact region of the substrate and over a part of the second dielectric region above the first FET gate, forming an opening through the first dielectric region extending to the contact region and the part of the second dielectric region, and filling the opening with a conductor making electrical connection with the contact region but electrically insulated from the first FET gate by the second dielectric region. A further FET gate may also be provided having an electrical contact thereto formed separately from the source-drain contact.

Integrated circuit contact structure and method

A method includes providing a semiconductor structure including a plurality of devices; depositing a nitride cap over the semiconductor structure; forming an aluminum mask over the nitride cap, the aluminum mask including a plurality of first openings; converting the aluminum mask to an aluminum oxide etch stop layer; and performing middle-of-line fabrication processing, leaving the aluminum oxide etch stop layer in place. A semiconductor structure includes a plurality of devices on a substrate; a nitride cap over the plurality of devices; an aluminum oxide etch stop layer over the nitride cap; an inter-level dielectric (ILD) over the aluminum oxide etch stop layer; and a plurality of contacts extending through the ILD, the aluminum oxide etch stop layer and the nitride cap to the plurality of devices.

Converting metal mask to metal-oxide etch stop layer and related semiconductor structure

The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal dielectric passivation stack positioned on at least the gate conductor sidewalls, the conformal dielectric passivation stack comprising a plurality of conformal dielectric layers, wherein no electrical path extends entirely through the stack; and a contact to the source and drain regions, wherein the discontinuous seam through the conformal dielectric passivation stack substantially eliminates shorting between the contact and the gate conductor. The present invention also provides a method for forming the above-described semiconducting device.

Barrier dielectric stack for seam protection

An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.

Edge seal for a semiconductor device

An on-chip redundant crack termination barrier structure, or crackstop, provides a barrier for preventing defects, cracks, delaminations, and moisture/oxidation contaminants from reaching active circuit regions. Conductive materials in the barrier structure design permits wiring the barriers out to contact pads and device pins for coupling a monitor device to the chip for monitoring barrier integrity.

Multi-functional structure for enhanced chip manufacturibility and reliability for low k dielectrics semiconductors and a crackstop integrity screen and monitor

Methods of etching a semiconductor structure using ion milling with a variable-position endpoint detector to unlayer multiple interconnect layers, including low-k dielectric films. The ion milling process is controlled for each material type to maintain a planar surface with minimal damage to the exposed materials. In so doing, an ion beam mills a first layer and detects an endpoint thereof using an optical detector positioned within the ion beam adjacent the first layer to expose a second layer of low-k dielectric film. Once the low-k dielectric film is exposed, a portion of the low-k dielectric film may be removed to provide spaces therein, which are backfilled with a material and polished to remove the backfill material and a layer of the multiple interconnect metal layers. Still further, the exposed low-k dielectric film may then be removed, and the exposed metal vias polished.

Method of reworking structures incorporating low-k dielectric materials

An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structure comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

Bilayer HDP CVD/PE CVD cap in advanced BEOL interconnect structures and method thereof

An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

Bilayer HDP CVD/PE CVD cap in advance BEOL interconnect structures and method thereof

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Hopewell Junction, NY, United States of America

Brett H Engel