Intel Corporation

Brett E Huff

Farhad K Moghadam

Oleh Karpenko

Michael A Maxim

Farshid Adibi-rizi

Philip E Freiberger

Ragupathy V Giridhar

William G Petro

Ken Schatz

Kenneth D Schatz

Farhad K Moghadom

Mike Maxim

Electron emission structures formed using standard semiconductor processes on a substrate first prepared with a topographical feature are disclosed. At least one layer of a first material is concurrently deposited on the substrate and etched from the substrate to form an atomically sharp feature. An at least one layer of a second material is deposited over the atomically sharp feature. A conductive layer is deposited over the at least one layer of the second material. A selected area of material is removed from the conductive layer and the at least one layer of second material to expose the atomically sharp feature. Finally, electrical connectivity is provided to elements of the electron emission structure.

Design structures of and simplified methods for forming field emission microtip electron emitters

A sputter etch system and a method of conducting a sputter etch. The sputter etch system includes an etch chamber with a wafer pedestal having a top surface to support a wafer and a magnet configured to provide a continuous magnetic field directed at the top surface of the wafer pedestal.

Approach to optimizing an ILD argon sputter process

Methods for forming microtips in a field emission device

A method of planarizing comprising providing a substrate having an uneven surface topography, forming a layer on the substrate, wherein the layer has a graded resistance to polishing, and polishing the layer.

Method of planarizing by polishing a structure which is formed to

A method for improving interlayer dielectric to metal layer adhesion including an in-situ plasma treatment process. A metal layer which is formed on a substrate is treated with plasma prior to the deposition of the interlayer dielectric. The interlayer dielectric is deposited above the metal layer and contacts are formed through the interlayer dielectric which electrically connect the underlying metal layer to a subsequently formed metal layer. The plasma treatment step creates open molecular bonds on the surface of the metal layer which cause the interface between the metal layer and the interlayer dielectric to become more adhesive. Thus, decreasing the likelihood of delamination that degrades the electrical reliability of the device.

In-situ pre-ILD deposition treatment to improve ILD to metal adhesion

A method of depositing an inter layer dielectric. A first layer using plasma enhanced chemical vapor deposition (CVD) is deposited. It is followed by a second layer, deposited using sub atmospheric CVD. The second layer is argon sputter etched.

DSAD process for deposition of inter layer dielectric

Deposition of an inter layer dielectric formed on semiconductor wafer by

A method of forming a device and the device itself that utilizes a high density plasma-enhanced TEOS-based intermetal dielectric is disclosed. The high density is accomplished though the use of higher RF power and higher oxygen flow rate so that the TEOS is more completely oxidized. The higher density intermetal dielectric absorbs water from air slower than a standard intermetal dielectric film. This lower water absorbance reduces the amount of water in the device and reduces hot electron induced device degradation.

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Fremont, CA, United States of America

Brett E Huff