Micron Technology Incorporated

Other

Brenda D Kraus

Eugene P Marsh

Richard H Lane

Timothy A Quick

John H Givens

Russell C Zahorik

John T Moore

John A Smythe

Jordan D Greenlee

Scott Jeffrey DeBoer

Rita J Klein

John Mark Meldrim

Everett Allen McTeer

Stefan Uhlenbrock

Michael Tristan Andreas

Christopher W Petz

Matthew N Rocklein

Sumeet C Pandey

David Ross Economy

Sanket S Kelkar

Dojun Kim

Yifen Liu

An-Jen B Cheng

Brian A Vaartstra

Donald L Westmoreland

James J Hofmann

Diana C Majerus

Richard Beeler

Ying Zhang

Soo Koon Ng

Methods and devices associated with providing access to a computing device are described. A method can include generating a real-time image including an attempted user, comparing the real-time image to a reference image of an authorized user, identifying an obstructed portion of the attempted user, comparing an unobstructed portion of the attempted user to a portion of the authorized user corresponding to the unobstructed portion of the attempted user, providing access to a computing device in response to the unobstructed portion of the attempted user matching the portion of the authorized user, and rejecting access to the computing device in response to the unobstructed portion of the attempted user being different from the portion of the authorized user.

Providing access to a computing device

Apparatuses, methods, and systems related to electrode formation are described. A first portion of a top electrode is formed over a dielectric material of a storage node. A metal oxide is formed over the first portion of the electrode. A second portion of the electrode is formed over the metal oxide.

Electrode formation

Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

Assemblies having conductive structures with three or more different materials

Methods and apparatuses associated with rebooting a computing device are described. Examples can include receiving at a processing resource of a computing device first signaling associated with boot programs of the computing device and second signaling associated with a boot sequence of the computing device. Examples can include writing from the processing resource to a memory resource data that is based at least in part on the first and the second signaling and writing from the processing resource to the memory resource data representative of activity of the computing device. Examples can include identifying data representative of a boot process for the computing device and rebooting the computing device in a particular sequence including the monitored activity, based at least in part on the data representative of the boot process responsive to a shutdown, restart, or both, of the computing device.

Computing device reboot

Methods of forming silicon nitride. Silicon nitride is formed on a substrate by atomic layer deposition at a temperature of less than or equal to about 275&#xb0; C. The as-formed silicon nitride is exposed to a plasma. The silicon nitride may be formed as a portion of silicon nitride and at least one other portion of silicon nitride. The portion of silicon nitride and the at least one other portion of silicon nitride may be exposed to a plasma treatment. Methods of forming a semiconductor structure are also disclosed, as are semiconductor structures and silicon precursors.

Methods of forming silicon nitride including plasma exposure

Methods, apparatuses, and systems related to forming a barrier material on an electrode are described. An example method includes forming a top electrode of a storage node on a dielectric material in a semiconductor fabrication sequence and forming, in-situ in a semiconductor fabrication apparatus, a barrier material on the top electrode to reduce damage to the dielectric material when ex-situ of the semiconductor fabrication apparatus.

Forming a barrier material on an electrode

Methods, apparatuses, and systems related to forming a barrier material between an electrode and a dielectric material are described. An example method includes forming a dielectric material on a bottom electrode material of a storage node in a semiconductor fabrication process. The method further includes forming a barrier material on the dielectric material to reduce oxygen vacancies in the dielectric material. The method further includes forming a top electrode on the barrier material.

Electrode/dielectric barrier material formation and structures

Methods of forming semiconductor devices comprising silicon nitride on high aspect ratio features

Methods of forming silicon nitride by atomic layer deposition and methods of forming semiconductor structures

Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge storage units in electronic structures for use in a wide range of electronic devices and systems. The isolated conductive nanoparticles may be used as a floating gate in a flash memory. In an embodiment, conductive nanoparticles are deposited on a dielectric layer by a plasma-assisted deposition process such that each conductive nanoparticle is isolated from the other conductive nanoparticles to configure the conductive nanoparticles as charge storage elements.

Conductive nanoparticles

Confined resistance variable memory cell structures and methods are described herein. One or more methods of forming a confined resistance variable memory cell structure includes forming a via in a memory cell structure and forming a resistance variable material in the via by performing a process that includes providing a germanium amidinate precursor and a first reactant to a process chamber having the memory cell structure therein and providing an antimony ethoxide precursor and a second reactant to the process chamber subsequent to removing excess germanium.

Confined resistance variable memory cell structures and methods

The use of a monolayer or partial monolayer sequencing process to form conductive titanium nitride produces a reliable structure for use in a variety of electronic devices. In an embodiment, a structure can be formed by using ammonia and carbon monoxide reactant materials with respect to a titanium-containing precursor exposed to a substrate. Such a TiN layer has a number of uses including, but not limited to, use as a diffusion barrier underneath another conductor or use as an electro-migration preventing layer on top of a conductor. Such deposited TiN material may have characteristics associated with a low resistivity, a smooth topology, high deposition rates, excellent step coverage, and electrical continuity.

Titanium nitride films

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Boise, ID, United States of America

Brenda D Kraus