Western Digital Corporation

Bradley S Masters

Randall M Chung

Disclosed is an improved logic circuit employing dynamic CMOS logic and having alternating logic employing first and second conductivity type transistors, respectively, separated by clocked inverters. The circuit employs a single clock signal to synchronize the dynamic logic operations of said logic gates and, along with a second, complement clock signal, said clocked inverters. Precharge transistors of each conductivity type are slowed slightly with respect to logic transistors, and the complement clock signal is delayed slightly with respect to the clock signal, thereby providing racefree logic operations. An implementation in a PLA is disclosed employing two logic planes for implementing arbitrary logic equations on input logic signals. The first logic plane and second logic plane are evaluated on separate phases of a complement clock signal and are separted by a clocked latch/inverter for providing correct logic evaluation between the logic planes.

CMOS circuit with racefree single clock dynamic logic

Disclosed is a programmable logic array employing dynamic CMOS logic and utilizing a single clock signal and its complement to synchronize said dynamic logic operations. The PLA disclosed employs two logic planes for implementing arbitrary logic equations on input logic signals. The first logic plane and second logic plane are evaluated on separate phases of a clock signal and its complement and are separated by a clocked latch/inverter for providing correct logic evaluation between the logic planes.

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Chino, CA, United States of America

Bradley S Masters