Micron Technology Incorporated

Bradley R Bitz

Xiao Li

Jaspreet Singh Gandhi

Todd O Bolken

Mark A Tverdy

João Elmiro Da Rocha Chaves

Kristopher D Hamrick

Scott Willmorth

Brandon P Wirz

Andrew M Bayless

Shams U Arifeen

Pei Sian Shao

Kaleb A Wilson

James J Oleary

Methods, systems, and devices for circuit board structures for component protection are described. A memory system may be implemented on a circuit board, where one or more memory devices may be attached to the circuit board. Components for accessing the one or more memory devices may also be attached to the circuit board. The circuit board may also include one or more structures extending from the circuit board that are configured to shield the one or more memory devices, the components for accessing the one or more memory devices, or both, from forces.

Circuit board structures for component protection

A printed wiring board is disclosed, with a build-up lamination material comprising a die side and a land side; a recess in the build-up lamination material at the die side, the recess comprising a recess floor; a first wall orthogonal to the recess floor; a second wall orthogonal to the recess floor, the second wall spaced apart from and opposite the first wall; a first recessed contact pad including a first vertical portion substantially in the recess at the first wall; a second recessed contact pad including a second vertical portion substantially in the recess at the second wall; and electrical coupling structures within the build-up lamination material, the electrical coupling structures coupled to each of the first recessed contact pad and the second recessed contact pad.

Printed wiring boards, printed wiring board assemblies, and electronic systems

Various embodiments described herein provide a label configured for thermal conductivity and configured to pass over an edge of a printed circuit board (PCB) and attached to both sides of the printed circuit board. The label can be used with a printed circuit board that is associated with a memory sub-system, such as a memory module (e.g., solid state drive, SSD module).

Thermally conductive label for circuit

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies and a package substrate carrying the first and second semiconductor dies. The second semiconductor die includes a first peripheral portion extending laterally outward beyond a first edge surface of the first semiconductor die. Similarly, the package substrate includes a second peripheral portion extending laterally outward beyond a second edge surface of the second semiconductor die. The semiconductor die assembly further includes a first volume of molded underfill material between the first and second semiconductor dies, a second volume of molded underfill material between the package substrate and the second semiconductor die, a first molded peripheral structure laterally adjacent to the first edge surface of the first semiconductor die, and a second molded peripheral structure laterally adjacent to the second edge surface of the second semiconductor die.

Semiconductor die assemblies having molded underfill structures and related technology

Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a base region, at least one second semiconductor die at the base region, and a thermal transfer device attached to the first and second dies. The thermal transfer device includes an encapsulant at least partially surrounding the second die and a via formed in the encapsulant. The encapsulant at least partially defines a cooling channel that is adjacent to a peripheral region of the first die. The via includes a working fluid and/or a solid thermal conductor that at least partially fills the channel.

Semiconductor device assembly with through-mold cooling channel formed in encapsulant

A method for separating semiconductor die stacks of a chip-on-wafer assembly is disclosed herein. In one example, divider walls are arranged in a pattern on a first surface of a device wafer such that regions between the divider walls define mounting sites. Die stacks are mounted to the device wafer, wherein individual die stacks are located at a corresponding mounting site between the divider walls. The device wafer is cut through from a second surface that is opposite the first surface of the device wafer, and the divider walls are removed from between the die stacks to form a vacant lane between adjacent die stacks.

Separation method and assembly for chip-on-wafer processing

Methods for fabricating microelectronic device assemblies, the method comprising providing mutually spaced stacks of microelectronic devices on a substrate and substantially concurrently encapsulating the stacks of microelectronic devices on the substrate and gang bonding mutually aligned conductive elements of vertically adjacent microelectronic devices. Compression molding apparatus for implementing the methods, and resulting microelectronic device assemblies are also disclosed.

Methods and apparatus for integrated gang bonding and encapsulation of stacked microelectronic devices

Method for manufacturing a semiconductor device assembly with through-mold cooling channel formed in encapsulant

A method of packaging imager devices and optics modules is disclosed which includes positioning an imager device and an optics module in each of a plurality of openings in a carrier body, introducing an encapsulant material into each of the openings in the carrier body and cutting the carrier body to singulate the plurality of imager devices and optics modules into individual units, each of which comprise an imager device and an optics module. A device is also disclosed which includes an imager device comprising a plurality of photosensitive elements and an optics module coupled to the imager device, the optics module comprising at least one lens that, when the optics module is coupled to the imager device, is positioned a fixed, non-adjustable distance from the plurality of photosensitive elements.

Growing community of inventors

Boise, ID, United States of America

Bradley R Bitz