Freescale Semiconductor,inc.

Motorola Corporation

Nxp Usa, Inc.

Freesacle Semiconductor, Inc.

Bradley Paul Smith

Edward Outlaw Travis, Jr

Mehul D Shroff

Ruiqi Tian

Sejal N Chheda

Suresh Venkatesan

James W Miller

Mohammed Rabiul Islam

Sam S Garcia

Dean J Denning

Thomas Sachio Kobayashi

Kevin G Kemp

Percy V Gilbert

Subramoney V Iyer

Brian George Anthony

Matthew A Thompson

Gregory Norman Hamilton

Rajive Dhar

Daniel J Loop

Md Rabiul Islam

An integrated circuit includes a first device having a first threshold voltage (Vt) adjusting implant extension region having a first conductivity type and extending from a first implant rail region under an entirety of a first channel region. The first implant rail region and first Vt adjusting implant extension region are contiguous, and the first channel region is over an insulating layer and the insulating layer is over the first implant rail region and first Vt adjusting implant extension region. A second device has a second Vt adjusting implant extension region having the first conductivity type and extending from a second implant rail region under an entirety of a second channel region. The second implant rail region and second Vt adjusting implant extension region are contiguous, and the second channel region is over the insulating layer and the insulating layer is over the second implant rail region and second Vt adjusting implant extension region.

Devices and methods for fully depleted silicon-on-insulator back biasing

An electronic device can include electronic components and an insulating layer overlying the electronic components. The electronic device can also include a capacitor overlying the insulating layer, wherein the capacitor includes a first electrode and a second electrode. The second electrode can include an opening, wherein from a top view, a defect lies within the opening. In another aspect, a process of forming an electronic device can include forming a first capacitor electrode layer over a substrate, forming a dielectric layer over the first capacitor electrode layer, and forming a second capacitor electrode layer over the dielectric layer. The process can also include detecting a defect and removing a first portion of the second capacitor electrode layer corresponding to the defect, wherein a second portion of the second capacitor electrode layer remains over the dielectric layer.

Electronic device including a capacitor and a process of forming the same

A mechanism is provided for extending useable lifetimes of semiconductor devices that are subject to trapped charge carriers in a gate dielectric. Embodiments of the present invention provide heat to the gate dielectric region from one or more sources, where the heat sources are included in a package along with the semiconductor device. It has been determined that heat, when applied during a period when the channel region of a transistor is in accumulation mode or is not providing a current across the channel, can at least partially recover the device from trapped charge carrier effects. Embodiments of the present invention supply heat to the affected gate dielectric region using mechanisms available where the semiconductor device is used (e.g., in the field).

Method and system for recovering from transistor aging using heating

A first dielectric layer is formed on a substrate in a transistor region and an NVM region, a first conductive layer is formed on the first dielectric layer, a second dielectric layer is formed on the first conductive layer, and a second conductive layer is formed over the second dielectric layer. A patterned etch is performed to remove at least a portion of the second conductive layer in the transistor region and to expose an extension portion of the first conductive layer. A first mask is formed over the transistor region having a first pattern, wherein the first pattern is of a gate stack of the MOSFET and an extension in the extension portion extending from the gate stack, and a second mask over the NVM region having a second pattern, wherein the second pattern is of a gate stack of the NVM cell. A patterned etch is then performed.

Patterning a gate stack of a non-volatile memory (NVM) with formation of a metal-oxide-semiconductor field effect transistor (MOSFET)

A gate-edge diode is made in a diode region of a substrate and a non-volatile memory cell is made in an NVM region of the substrate. A first dielectric layer is formed on the substrate in the diode region and the NVM region. A first conductive layer is formed on the first dielectric layer. A second dielectric layer is formed on the first conductive layer. A second conductive layer is formed over the second dielectric layer. A first mask is formed over the diode region having a first pattern. The first pattern is of a plurality of fingers and a second mask over the NVM region has a second pattern. The second pattern is of a gate stack of the non-volatile memory cell. An etch is performed through the second conductive layer, the second dielectric layer, and the first conductive layer to leave the first pattern of the plurality of fingers in the diode region and the second pattern of the gate stack in the NVM region. An implant is performed using the gate stack and the plurality of fingers as a mask to provide source/drain regions adjacent to the gate stack in the NVM region and diode terminals between the fingers in the diode region to form the gate-edge diode with the diode terminals and the substrate.

Patterning a gate stack of a non-volatile memory (NVM) with formation of a gate edge diode

A capacitor and an NVM cell are formed in an integrated fashion so that the etching of the capacitor is useful in end point detection of an etch of the NVM cell. This is achieved using two conductive layers over an NVM region and over a capacitor region. The first conductive layer is patterned in preparation for a subsequent patterning step which includes a step of patterning both the first conductive layer and the second conductive layer in both the NVM region and the capacitor region. The subsequent etch provides for an important alignment of a floating gate to the overlying control gate by having both conductive layers etched using the same mask. During this subsequent etch, the fact that first conductive material is being etched in the capacitor region helps end point detection of the etch of the first conductive layer in the NVM region.

Patterning a gate stack of a non-volatile memory (NVM) with formation of a capacitor

In one embodiment, a method of forming a via includes providing a semiconductor substrate, wherein the semiconductor substrate comprises a through-via region, forming isolation openings and a sacrificial feature in the through-via region, filling the isolation openings to form isolation regions, forming a dielectric layer over the semiconductor substrate after filling the isolation openings, forming a first portion of a through-via opening in the dielectric layer, forming a second portion of the through-via opening in the semiconductor substrate, wherein forming the second portion of the through-via opening comprises removing the sacrificial feature, and forming a conductive material in the first portion and the second portion of the through-via opening.

Through-via and method of forming

In one embodiment, a method of forming a via includes forming an first opening in the semiconductor substrate, wherein the first opening has a bottom and sidewalls, forming a sacrificial fill in the first opening, forming a dielectric layer over the sacrificial fill, forming a second opening in the dielectric layer, wherein the second opening is over the sacrificial fill, removing the sacrificial fill from the first opening after forming the second opening, and forming a conductive material in the first opening and second opening.

A test circuit tests a device under test (DUT) uses a first switching device and a second switching device. The device under test (DUT) has a terminal for receiving a test signal. The first switching device has an output terminal for use in coupling the test signal to the terminal of the DUT when the DUT is being tested. The first switching device is high impedance when the DUT is not being tested. The second switching device is high impedance when the DUT is being tested and couples a bias control signal to the output terminal of the first switching device when the DUT is not being tested. The bias control signal substantially tracks the test signal. Leakage from the first switching device when other DUTs are being tested is greatly reduced because the bias control signal results in little or no bias across the first switching device.

Semiconductor device test system having reduced current leakage

A semiconductor device that has a common border between P and N wells is susceptible to photovoltaic current that is believed to be primarily generated from photons that strike this common border. Photons that strike the border are believed to create electron/hole pairs that separate when created at the PN junction of the border. The photovoltaic current can have a sufficient current density to be destructive to the metal connections to a well if the area of these metal connections to the well is small relative to the length of the border. This photovoltaic current can be reduced below destructive levels by covering the common border sufficiently to reduce the number of photons hitting the common border. The surface area of the connections can also be increased to alleviate the problem.

Semiconductor device for reducing photovolatic current

A process for forming a masking database that includes defining a first feature level for the masking database corresponding to a first layer. The first feature level includes a first region with a first feature density and a second region with a second feature density that is substantially different from the first feature density. The process also includes defining a second feature level for the masking database corresponding to a second layer, wherein the second feature level is to be formed over a substrate after the first feature level has been formed over or within the substrate. A first feature within the second feature level will be formed within the first region, a second feature within the second feature level will be formed within the second region. The second layer will have a first thickness over the first layer within the first region and has a second thickness over the first layer within the second region. At least one of the first and second features is adjusted to at least partially compensate for a difference between the first and second thicknesses.

Selective sizing of features to compensate for resist thickness variations in semiconductor devices

At least one process-assist feature ( ) at or near a via location of a wiring structure ( ) within a semiconductor device is used to improve processing or processing margin during subsequent processing. For at least some of the embodiments of the present invention, the process-assist features feature ( ) help to make a flowable layer more uniform over via locations ( ). Typically, this can help in the formation of via openings. When a resist layer ( ) is formed over the process-assist features, the resist layer ( ) will have a more uniform thickness over most via locations within the device. When an insulating layer ( ) is formed over the via locations, the insulating layer ( ) will have a more uniform thickness over most via locations within the device. More control during resist exposure or via opening etching allow more process margin. The embodiments described herein illustrate the flexibility in placing process-assist features.

Semiconductor device, a process for a semiconductor device, and a process for making a masking database

A method for forming an improved copper inlaid interconnect (FIG. ) begins by performing an RF preclean operation ( ) on the inlaid structure in a chamber ( ). The RF preclean rounds corners ( and ) of the structure to reduce voiding and improve step coverage while not significantly removing copper atoms from the underlying exposed copper interconnects surfaces ( ). A tantalum barrier ( ) is then deposited where one portion of the tantalum barrier is more tensile than another portion of the tantalum barrier. After formation of the barrier layer ( ), a copper seed layer ( ) is formed over a top of the barrier layer. The copper layer is formed while clamping the wafer with an improved clamp ( ) which reduces copper peeling and contamination at wafer edges. Copper electroplating and chemical mechanical polishing (CMP) processes are then used to complete the copper interconnect structure.

Method of forming a semiconductor device barrier layer

A dual inlaid copper interconnect structure uses a plasma enhanced nitride (PEN) bottom capping layer and a silicon rich silicon oxynitride intermediate etch stop layer. The interfaces (,, and,) between these layers (,and,) and their adjacent dielectric layers (,and,) are positioned in the stack (,) independent of the desired aspect ratio of trench openings of the copper interconnect in order to improve optical properties of the dielectric stack (,). Etch processing is then used to position the layers (,) and (,) at locations within the inlaid structure depth that result in one or more of reduced DC leakage current, improved optical performance, higher frequency of operation, reduced cross talk, increased flexibility of design, or like improvements.

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Austin, TX, United States of America

Bradley Paul Smith