International Business Machines Corporation

Bradley Alan Orner

Robert Mark Rassel

David Charles Sheridan

Jeffrey Bowman Johnson

Xuefeng Liu

Alvin Jose Joseph

Douglas Duane Coolbaugh

Qizhi Liu

Zhong-Xiang He

Vidhya Ramachandran

Natalie Barbara Feilchenfeld

Stephen Arthur St Onge

Benjamin T Voegeli

Steven H Voldman

Wagdi William Abadeer

Rajendran Krishnasamy

Michael Joseph Zierak

Louis DeWolf Lanzerotti

David S Collins

Peter John Geiss

Eric Adler

Barbara Ann Waterhouse

Wade J Hodge

Jay S Rascoe

Edward J Nowak

Jeffrey P Gambino

Ping-Chuan Wang

Mark David Jaffe

Marwan H Khater

Scott Kevin Reynolds

James Spiros Nakos

Andreas Daniel Stricker

Brian Allan Floyd

Peter James Lindgren

Ramana Murty Malladi

David R Greenberg

Mattias E Dahlstrom

Robert L Barry

Phillip Francis Chapman

Kevin N Ogg

Michael Lawrence Gautsch

Disclosed are guard ring structures with an electrically insulated gap in a substrate to reduce or eliminate device coupling of integrated circuit chips, methods of manufacture and design structures. The method includes forming a guard ring structure comprising a plurality of metal layers within dielectric layers. The method further includes forming diffusion regions to electrically insulate a gap in a substrate formed by segmented portions of the guard ring structure.

Segmented guard ring structures with electrically insulated gap structures and design structures thereof

A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.

Silicon germanium (SiGe) heterojunction bipolar transistor (HBT)

A method for forming a Schottky barrier diode on a SiGe BiCMOS wafer, including forming a structure which provides a cutoff frequency (F) above about 1.0 THz. In embodiments, the structure which provides a cutoff frequency (F) above about 1.0 THz may include an anode having an anode area which provides a cutoff frequency (F) above about 1.0 THz, an n-epitaxial layer having a thickness which provides a cutoff frequency (F) above about 1.0 THz, a p-type guardring at an energy and dosage which provides a cutoff frequency (F) above about 1.0 THz, the p-type guardring having a dimension which provides a cutoff frequency (F) above about 1.0 THz, and a well tailor with an n-type dopant which provides a cutoff frequency (F) above about 1.0 THz.

Schottky barrier diodes for millimeter wave SiGe BiCMOS applications

High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces.

Bipolar transistor with raised extrinsic self-aligned base using selective epitaxial growth for BiCMOS integration

Radio frequency integrated circuits with on-chip noise source for use in the performance of tests and/or calibrations. A radio frequency integrated circuit includes at least one noise source residing on the radio frequency integrated circuit, the noise source being controllable by a digital input, and a radio frequency circuit residing on the radio frequency integrated circuit and being coupled to the noise source, wherein at least one attribute of the radio frequency circuit is determinable by controlling the noise source via the digital input.

Radio frequency integrated circuit with on-chip noise source for self-test

A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.

Silicided trench contact to buried conductive layer

Silicon germanium heterojunction bipolar transistor having interstitial trapping layer in base region

A method for forming a lateral passive device including a dual annular electrode is disclosed. The annular electrodes formed from the method include an anode and a cathode. The annular electrodes allow anode and cathode series resistances to be optimized to the lowest values at a fixed device area. In addition, the parasitic capacitance to a bottom plate (substrate) is greatly reduced.

Lateral passive device having dual annular electrodes

The embodiments of the invention provide a structure, method, etc. for a fin differential MOS varactor diode. More specifically, a differential varactor structure is provided comprising a substrate with an upper surface, a first vertical anode plate, and a second vertical anode plate electrically isolated from the first vertical anode plate. Moreover, a semiconductor fin comprising a cathode is between the first vertical anode plate and the second vertical anode plate, wherein the semiconductor fin, the first vertical anode plate, and the second vertical anode plate are each positioned over the substrate and perpendicular to the upper surface of the substrate.

FIN differential MOS varactor diode

A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.

Deep trench based far subcollector reachthrough

Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.

Varied impurity profile region formation for varying breakdown voltage of devices

The structure for millimeter-wave frequency applications, includes a Schottky barrier diode (SBD) with a cutoff frequency (F) above 1.0 THz formed on a SiGe BiCMOS wafer. A method is also contemplated for forming a Schottky barrier diode on a SiGe BiCMOS wafer, including forming a structure which provides a cutoff frequency (F) above about 1.0 THz. In embodiments, the structure which provides a cutoff frequency (F) above about 1.0 THz may include an anode having an anode area which provides a cutoff frequency (F) above about 1.0 THz, an n-epitaxial layer having a thickness which provides a cutoff frequency (F) above about 1.0 THz, a p-type guardring at an energy and dosage which provides a cutoff frequency (F) above about 1.0 THz, the p-type guardring having a dimension which provides a cutoff frequency (F) above about 1.0 THz, and a well tailor with an n-type dopant which provides a cutoff frequency (F) above about 1.0 THz.

Schottky barrier diodes for millimeter wave SiGe BICMOS applications

An improved bipolar transistor with dual shallow trench isolation for reducing the parasitic component of the base to collector capacitance Ccb and base resistance Rb is provided. The structure includes a semiconductor substrate having at least a pair of neighboring first shallow trench isolation (STI) regions disposed therein. The pair of neighboring first STI regions defines an active area in the substrate. The structure also includes a collector disposed in the in the active area of the semiconductor substrate, a base layer disposed atop a surface of the semiconductor substrate in the active area, and a raised extrinsic base disposed on the base layer. In accordance with the present, the raised extrinsic base has an opening to a portion of the base layer. An emitter is located in the opening and extending on a portion of the patterned raised extrinsic base; the emitter is spaced apart and isolated from the raised extrinsic base. Moreover, and in addition to the first STI region, a second shallow trench isolation (STI) region is present in the semiconductor substrate which extends inward from each pair of said first shallow trench isolation regions towards said collector. The second STI region has an inner sidewall surface that is sloped. In some embodiments, the base is completely monocrystalline.

Bipolar transistor with dual shallow trench isolation and low base resistance

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Fairfax, VT, United States of America

Bradley Alan Orner