Taiwan Semiconductor Manufacturing Comp. Ltd.

Boson Lin

Ching-Wen Cho

David Ho

A split-gate flash memory cell having a spacer-like floating gate is disclosed as well as a method of forming the same. This is accomplished by defining a floating area opening in a structure layer over a substrate, and forming polysilicon spacers along the vertical walls of the opening. Then an intergate oxide is formed over the spacer-like floating gates followed by the forming of individual control gates. Thus, a flash memory is formed having two independent cells with their own spacer floating gates and control gates sharing one source with the capability of being shrunk in size much more readily than conventionally possible.

Spacer like floating gate formation

A semiconductor EEPROM device and a method for making it are achieved. The EEPROM device is a novel twin-bit cell structure with adjacent floating gates having a common control gate and common bit-line contact in each cell area. In each cell area a first and second floating gate is formed. Source areas are formed in the substrate adjacent to the outer edges of the floating gates and a drain area is formed between and adjacent to the floating gates. A gate oxide is formed over the floating gates. A control gate is formed over the drain area and patterned to also partially extend over the floating gates. The control gate is also patterned to provide a recess for a bit-line contact to the drain area. The recess results in reduced cell area and the non-critical overlay of the control gate over the floating gates results in relaxed overlay alignment.

Twin-bit memory cell having shared word lines and shared bit-line contacts for electrically erasable and programmable read-only memory (EEPROM) and method of manufacturing the same

Within a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is employed at least one of: (1) an annular shaped floating gate electrode formed with a spacer shaped cross-section having a tip at its upper outer periphery; and (2) a pair of source/drain regions formed into a semiconductor substrate adjacent a pair of opposite sides of the annular shaped floating gate electrode, where one of the pair of source/drain regions is formed further beneath the annular shaped floating gate electrode than the other of the pair of source/drain regions. The split gate field effect transistor (FET) device is formed with enhanced properties, such as decreased dimensions and enhanced coupling.

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Hsin-Chu, Taiwan

Boson Lin