Siliconix Incorporated

Tru-si Technologies, Inc.

Bosco Lan

Yueh-Se Ho

Oleg Siniaguine

Sergey Savastiouk

Sam Kao

Patrick A Halahan

Anup Bhalla

Fwu-Iuan Hshieh

Jacek Korec

Y Mohammed Kasem

Jowei Dun

Eddy Tjhia

Chang-Sheng Chen

Lee Shawn Luo

A through hole () is formed in a wafer () comprising a semiconductor substrate (). A seed layer () is sputtered on the bottom surface of the wafer. The seed is not deposited over the through hole's sidewalls adjacent the top surface of the wafer. A conductor () is electroplated into the through hole. In another embodiment, a seed is deposited into an opening in a wafer through a dry film resist mask (). The dry film resist overhangs the edges of the opening, so the seed is not deposited over the opening's sidewalls adjacent the top surface of the wafer. In another embodiment, a dielectric () is formed in an opening in a semiconductor substrate () by a non-conformal physical vapor deposition (PVD) process that deposits the dielectric on the sidewalls but not the bottom of the opening. A seed () is formed on the bottom by electroless plating. A conductor () is electroplated on the seed. In another embodiment, a dielectric () is formed in the opening to cover the entire surface of the opening. A non-conformal layer () is deposited by PVD over the sidewalls but not the bottom of the opening. The dielectric () is etched off the bottom with the non-conformal layer () as a mask. A seed () is formed on the bottom by electroless plating. The non-conformal layer can be formed by electroplating. It can be tantalum deposited by electroplating, then anodized. Other embodiments are also provided.

Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby

In a semiconductor package for a chip having terminals on both sides, for example, a power MOSFET in which the gate and source terminals are on the front side and the drain terminal is on the back side, electrical contact is made with the back side terminal by extending vias, which can take the form of trenches, holes or other cavities, either entirely or patrially through the chip. The vias are filled with a metal or other electrically conductive material. The process is performed on the chips in a wafer simultaneously. The resulting package is compact and economical to manufacture and can readily be mounted, flip-chip style, on a printed circuit board.

Vertical structure for semiconductor wafer-level chip scale packages

A method for forming a trenched DMOS transistor with deep body regions that occupy minimal area on an epitaxial layer formed on a semiconductor substrate. A first oxide layer is formed over the epitaxial layer and patterned to define deep-body areas beneath which the deep body regions are to be formed. Next, diffusion-inhibiting regions of the first conductivity type are formed in each of the deep-body areas before forming a second oxide layer covering the deep-body areas and the remaining portion of the first oxide layer. Portions of the second oxide layer are then removed to expose the centers of the diffusion inhibiting regions, leaving the first oxide layer and oxide sidewall spacers from the second oxide layer to cover the peripheries of the diffusion-inhibiting regions. A deep-body diffusion of a second conductivity type is then performed, resulting in the formation of deep body regions in the epitaxial layer between the sidewall spacers. The peripheries of the diffusion-inhibiting regions covered by the remaining portions of the first and second oxide layers inhibit lateral diffusion of the deep body diffusions without significantly inhibiting diffusion depth.

Fabrication of high-density trench DMOS using sidewall spacers

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Fremont, CA, United States of America

Bosco Lan