Syntest Technologies, Inc.

Boryau (Jack) Sheu

Laung-Terng (l-t) Wang

Shianling Wu

Khader S Abdel-Hafez

Xiaoqing Wen

Zhigang Jiang

Zhigang Wang

Shun-Miin (Sam) Wang

Laung-Terng Wang

Shyh-Horng Lin

Nur A Touba

Fei-Sheng Hsu

Augusli Kifli

Ming-Tung Chang

A pipelined scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.

Method and apparatus for pipelined scan compression

A method and apparatus for compacting test responses containing unknown values in a scan-based integrated circuit. The proposed X-driven compactor comprises a chain-switching matrix block and a space compaction logic block. The chain-switching matrix block switches the internal scan chain outputs before feeding them to the space compaction logic block for compaction so as to minimize X-induced masking and error masking. The X-driven compactor further selectively includes a finite-memory compaction logic block to further compact the outputs of the space compaction logic block.

Compacting test responses using X-driven compactor

A method and apparatus for selectively masking off unknown ('x') captured scan data in first selected scan cellsfrom propagating through the scan chainsfor test, debug, diagnosis, and yield improvement of a scan-based integrated circuitin a selected scan-test modeor selected self-test mode. The scan-based integrated circuitcontains a plurality of scan chains, a plurality of pattern generators, a plurality of pattern compactors, with each scan chaincomprising multiple scan cellscoupled in series. The method and apparatus further includes an output-mask controllerand an output-mask networkembedded on the scan data input path of second selected scan cells, or a set/reset controller controlling selected set/reset inputs of second selected scan cells. A synthesis method is also proposed for synthesizing the output-mask controllerand the set/reset controller.

Mask network design for scan-based integrated circuits

A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit. The scan architecture used can also be random access scan based, where the integrated circuit comprises an array of random access scan (RAS) cells that are randomly and uniquely addressable. In random access scan, test patterns can be applied by selectively updating RAS cells and test responses can be observed through a direct read-out process. Eliminating the shifting process inherent in serial scan, random access scan produces much lower test power dissipation than serial scan.

Method and apparatus for broadcasting test patterns in a scan-based integrated circuit

A pipelined scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. A decompressor is embedded between N scan chains and M scan chains, where N&#x3c;M, to broadcast compressed scan data patterns driven through the N scan chains into decompressed scan data patterns stored in the M scan chains. To speed up the shift-in/shift-out operation during decompression, the decompressor can be further split into two or more pipelined decompressors each placed between two sets of intermediate scan chains. The invention further comprises one or more pipelined compressors to speed up the shift-in/shift-out operation during compression.

A method and apparatus time-division demultiplexes and decompresses a compressed input stimulus provided at a selected data rate R1, into a decompressed stimulus, driven at a selected data rate R2, for driving selected scan chains in a scan-based integrated circuit using a plurality of time-division demultiplexors and time-division multiplexors for shifting stimuli and test responses in and out of high-speed I/O pads in order to reduce test time, test cost, and scan pin count. A synthesis method is also proposed for synthesizing the time-division multiplexors, decompressors, compressors, and time-division multiplexors.

Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit

Method and apparatus for broadcasting test patterns in a scan based integrated circuit

A multi-level scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The scan-based integrated circuit contains one or more scan chains, each scan chain including one or more scan cells coupled in series. Two or more decompressors are embedded between N compressed scan inputs and M scan chains, where N&#x3c;M, to broadcast compressed scan data patterns driven through the N compressed scan inputs into decompressed scan data patterns stored in the M scan chains. The multi-level scan compression approach allows to speed up the shift-in/shift-out operation during decompression using two or more decompressors separated by intermediate scan chains. Two or more compressors are separated by intermediate scan chains to speed up the shift-in/shift-out operation during compression.

Method and apparatus for multi-level scan compression

A method for performing ATPG (automatic test pattern generation) and fault simulation in a scan-based integrated circuit, based on a selected clock order in a selected capture operation, in a selected scan-test mode or a selected self-test mode. The method comprises compilingthe RTL (register-transfer level) or Gate-Level HDL (hardware description language) codebased on the Input Constraintsand a Foundry Library, into a Sequential Circuit Model. The Sequential Circuit Modelis then transformedinto an equivalent Combinational Circuit Modelfor performing Forward and/or Backward Clock Analysisto determine the driving and observing clocks for all inputs and outputs of all combinational logic gates in the Combinational Circuit Model. The analysis results are used for Uncontrollable/Unobservable Labelingof selected inputs and outputs of the combinational logic gates. Finally, ATPG and/or Fault Simulationare performed according to the Uncontrollable/Unobservable Labelingto generate the HDL Test Benches and ATE Test Programs

Method for performing ATPG and fault simulation in a scan-based integrated circuit

A method for generating stimuli and test responses for testing faults in a scan-based integrated circuit in a selected scan-test mode or a selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, N clock domains, and C cross-clock domain blocks, each scan chain comprising multiple scan cells coupled in series, each clock domain having one capture clock, each cross-clock domain block comprising a combinational logic network. The method comprises compiling the scan-based integrated circuit into a sequential circuit model; specifying input constraints on the scan-based integrated circuit during a shift and capture operation; specifying a clock grouping to map the N clock domains into G clock domain groups, where N&#x3e;G&#x3e;1; transforming the sequential circuit model into an equivalent combinational circuit model according to the input constraints and the clock grouping; and generating the stimuli and test responses on the equivalent combinational circuit model according to the input constraints.

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San Jose, CA, United States of America

Boryau (Jack) Sheu