Taiwan Semiconductor Manufacturing Comp. Ltd.

Bor-Zen Tien

Tzong-Sheng Chang

Kuang-Hsin Chen

Kang-Min Kuo

Chen-Chung Lai

Tsung-Yu Chiang

Han-Wei Yang

Ying-Chieh Liao

Song-Bor Lee

Cheng-Yi Peng

Yen-Ming Peng

Wen-Hsing Hsieh

Jon-Hsu Ho

Wen-Yuan Chen

Yi-Ruei Lin

Chen Kuang-Hsin

Mu-Yi Lin

Chung-Wei Lin

Hsuan-Han Lin

Gwo-Chyuan Kuoh

Chin-Chia Chang

Jhu-Ming Song

Yi-Ju Hsu

Che-Chia Hsu

Jieh-Ting Chang

Jung-Ting Chen

Chung-Wei Hung

Ying-Hua Lai

Yung-Fu Shen

Ting Tsai

Chia-Ming Chang

Wei-Shuo Ho

Chen Cheng Chou

Chen-Cheng Chou

Wen-Jye Yue

Shih-Chang Huang

Hung-Chi Tsai

Sheng-Ching Chen

A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.

Method of manufacturing semiconductor devices and semiconductor devices

A semiconductor device, includes a channel region, and a source/drain region adjacent to the channel region. The source/drain region includes a first epitaxial layer, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer, and the first epitaxial layer is made of SiAs.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a channel region, a source/drain region adjacent to the channel region, and a source/drain epitaxial layer. The source/drain epitaxial layer includes a first epitaxial layer epitaxially formed on the source/drain region, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer. The first epitaxial layer includes at least one selected from the group consisting of a SiAs layer, a SiC layer and a SiCP layer.

Method of manufacturing a semiconductor device and a semiconductor device

An apparatus includes a plurality of interconnect structures over a substrate, a dielectric layer formed over a top metal line of the plurality of interconnect structures, a first barrier layer on a bottom and sidewalls of an opening in the dielectric layer, wherein the first barrier layer is formed of a first material and has a first thickness, a second barrier layer over the first barrier layer, wherein the second barrier layer is formed of a second material different from the first material and has a second thickness and a pad over the second barrier layer, wherein the pad is formed of a third material.

Method for forming interconnect structure

Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.

Methods for manufacturing semiconductor arrangements using photoresist masks

Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.

Systems and methods to enhance passivation integrity

Back-end-of-line (BEOL) arrangement with multi-height interlayer dielectric (ILD) structures

Embodiments of the present disclosure relate generally to a semiconductor device and method of fabricating the same, the semiconductor device includes a semiconductor substrate and a gate stack disposed over a channel region of the semiconductor device, the gate stack includes an oxidation layer, a gate dielectric and a gate electrode, the oxidation layer at least covers a portion of the channel region of the semiconductor device and may act as a barrier to prevent damage to the underlying features, such as the source and drain regions, during removal of a dummy gate in a gate last process.

Semiconductor device and method of fabricating the same

A semiconductor device is provided. The semiconductor device includes a doped isolation structure formed above a substrate, and the doped isolation structure includes a first doped portion and a second doped portion, and a doped concentration of the second doped portion is different from a doped concentration of the first doped portion. The semiconductor device also includes a first fin partially embedded in the doped isolation structure, and a sidewall surface of the first fin is in direct contact with the first doped portion. The semiconductor device includes a second fin partially embedded in the doped isolation structure, and the doped isolation structure is between the first fin and the second fin, and a sidewall surface of the second fin is in direct contact with the second doped portion.

Mechanisms for forming FinFETs with different fin heights

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Hsinchu, Taiwan

Bor-Zen Tien