Freescale Semiconductor,inc.

Nxp Usa, Inc.

Boon Yew Low

Navas Khan Oratti Kalandar

Poh Leng Eu

Lan Chu Tan

Nishant Lakhera

Weng Hoong Chan

Fernando A Santos

Wai Yew Lo

Sheila F Chopin

Wai Keong Wong

Kesvakumar V C Muniandy

Ly Hoon Khoo

Chin Teck Siong

Teck Beng Lau

Vemal Raja Manikam

Fui Yee Lim

Vittal Raja Manikam

Li Li

Chee Seng Foong

Burton Jesse Carpenter

Kai Yun Yow

Akhilesh Kumar Singh

Seng Kiong Teng

Yin Kheng Au

Jia Lin Yap

Shufeng Zhao

Sharon Huey Lin Tay

Tzu Ling Wong

Dominic (PohMeng) Koey

Ngak Thong Teo

Ahmad Termizi Suhaimi

Vermal Raja Manikam

A circuit module includes a module substrate with a mounting surface, and a plurality of conductive features and electronic circuitry coupled to the mounting surface. Encapsulant material covers the electronic circuitry and the mounting surface, and an upper surface of the encapsulant material defined a first surface of the circuit module. A plurality of leadframe terminals, each separated from a non-planar leadframe unit, extend from the conductive features at the mounting surface through the encapsulant material toward the first surface of the circuit module. Each of the leadframe terminals is formed from an elongated planar conductive feature of a leadframe unit, and the plurality of leadframe terminals is electrically coupled to the electronic circuitry through the conductive features and the module substrate. Encapsulant divots may extend into the encapsulant material from the first surface of the circuit module, and proximal ends of the leadframe terminals terminate at the encapsulant divots.

Circuit modules with encapsulant-embedded leadframe terminals, and methods of fabricating such circuit modules

An encapsulant compound apparatus, includes a mechanical operator, and an insert disposed on a surface of the mechanical operator. The insert operates to capture foreign material in the encapsulant compound.

Conduit inserts for encapsulant compound formulation kneading and encapsulation back-end assembly processes

A circuit module (e.g., an amplifier module) includes a module substrate, a thermal dissipation structure, a semiconductor die, encapsulant material, and an interposer. The module substrate has a mounting surface and a plurality of conductive pads at the mounting surface. The thermal dissipation structure extends through the module substrate, and a surface of the thermal dissipation structure is exposed at the mounting surface of the module substrate. The semiconductor die is coupled to the surface of the thermal dissipation structure. The encapsulant material covers the mounting surface of the module substrate and the semiconductor die, and a surface of the encapsulant material defines a contact surface of the circuit module. The interposer is embedded within the encapsulant material. The interposer includes a conductive terminal with a proximal end coupled to a conductive pad of the module substrate, and a distal end exposed at the contact surface of the circuit module.

Circuit modules with front-side interposer terminals and through-module thermal dissipation structures

A packaged semiconductor device includes a substrate having input/output (I/O) pads, a semiconductor die attached to the substrate and electrically connected to the substrate with bond wires. A bond-wire reinforcement structure is formed over the bond wires before the assembly is covered with a molding compound. The bond-wire reinforcement structure prevents wire sweep during molding and protects the wires from shorting with other wires. In one embodiment, the bond-wire reinforcement structure is formed with a fiberglass and liquid epoxy mixture.

Semiconductor device with bond wire reinforcement structure

A package device has a first lead frame having a first flag. A first integrated circuit is on the first flag. A first encapsulant is over the first integrated circuit. A first plurality of leads is electrically bonded to the first integrated circuit. A first lead of the first plurality of leads has an inner portion covered by the first encapsulant and an outer portion extending outside the encapsulant. The outer portion has a hole and a bend at the hole. The outer portion extends above the first encapsulant.

Packaged semiconductor device having bent leads and method for forming

A packaged integrated circuit (IC) device includes a flexible substrate having contact pads, an IC die mounted on the substrate and electrically connected to the contact pads, and conductive threads sewn into the substrate. The conductive threads have proximal ends electrically connected to corresponding ones of the contact pads with conductive bumps. The conductive threads eliminate the need for a complicated multi-layer substrate structure for interconnect fan-out so the substrate may be formed of a variety of materials such as cloth or paper.

Integrated circuit with sewn interconnects

A method of forming a multilayer device includes providing a core substrate having opposing first and second core surfaces and forming top and bottom inner conductive patterns on each of the first and second core surfaces, respectively. A first dielectric layer is formed on the first core surface, and the top inner conductive pattern. A second dielectric layer is formed on the second core surface, and the bottom inner conductive pattern. The first and second dielectric layers are laminated with top and bottom outer conductive layers, respectively. A first via is provided through the core substrate extending from the top outer conductive layer to the bottom outer conductive layer. The first via is filled with solder. Magnetic particles are attracted by a magnetic force into the first via.

Method for forming multilayer device having solder filled via connection

A method of assembling a semiconductor package includes attaching a semiconductor die to a frame having a strip or panel form. The semiconductor die has at least one stud bump. The die and the stud bump are covered with a first encapsulation material, and then at least a portion of the stud bump is exposed. At least one die conductive member is formed on the first encapsulation material and electrically coupled to the stud bump. The die conductive member is covered with a second encapsulation material, and then at least a portion of the die conductive member is exposed. At least one grid array conductive member is formed on the second encapsulation material and electrically coupled to the die conductive member. Finally, at least one solder ball is attached to the at least one grid array conductive member.

Embedded die ball grid array package

A sub-assembly for a packaged integrated circuit (IC) device has a planar substrate. The substrate's top side has multiple sets electrically connected bond posts arranged in corresponding nested contour zones. Each contour zone includes a different bond post of each bond-post set. The bottom side has a different set of pad connectors electrically connected to the each top-side bond-post set. The sub-assembly can be used for different IC packages having IC dies of different sizes, with different contours of bond posts available for electrical connection depending on the size of the IC die.

Multi-use substrate for integrated circuit

A semiconductor device package such a as Ball Grid Array (BGA), includes a die attached to a substrate. The substrate has a series of plated through holes (PTH) that include a copper pad at each of their ends. The PTH are located in a mold gate region at a corner of the substrate beyond the periphery of the die. Each PTH contains a rivet. The PTH with the pads and rivets stabilize the substrate at the mold gate region, which reduces the possibility of substrate delamination upon degating following an encapsulation process.

Semiconductor device with plated through holes

Electrically conductive pillars with a solder cap are formed on a substrate with an electroplating process. A flip-chip die having solder wettable pads is attached to the substrate with the conductive pillars contacting the solder wettable pads.

Copper pillar bump and flip chip package using same

A semiconductor package has a substrate with a solder mask layer, and upper and lower surfaces. Conductive traces and electrical contacts are formed on the substrate, and vias are formed in the substrate to electrically connect the conductive traces and electrical contacts. A semiconductor die is attached on the upper surface of the substrate. A mold cap is formed on the upper surface of the substrate and covers the die and the conductive traces. The mold cap includes a mold body having clipped corners and extensions that extend from each of the clipped corners. The extensions and clipped corners help prevent package cracking.

Mold cap for semiconductor device

A Quad Flat Pack (QFP) type semiconductor device includes four corner tie bars that, instead of being trimmed, are used for power and/or ground connections, and alternatively, to control mold flow during the encapsulation step of the assembly process.

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Petaling Jaya, Malaysia

Boon Yew Low