Texas Instruments Corporation

Boon Pew Chan

Min Yu Chan

Kian Teng Eng

Chee Kiang Yew

Jing Sua Goh

Siu Waf Low

Pak Hong Yee

Tuck Fook Toh

Pang Hup Ong

Chew Weng Leong

Jeffrey Tuck Fook Toh

A high density unit ( ) comprising a first integrated circuit package ( ) comprising a carrier ( ) having first and second sides ( ), a silicon chip ( ) attached by an adhesive layer ( ) and solder bonding ( ) electrically connecting the silicon chip ( ) to the carrier ( ) stackably and electrically connected to a second integrated circuit package ( ), is disclosed.

Method of fabricating thin integrated circuit units

A method and apparatus for producing an integrated circuit package ( ) comprising a substrate ( ) having an opening ( ) and first and second surfaces ( ), a plurality of routing strips ( ) being integral with the substrate ( ) and extending into the opening ( ), a plurality of pads ( ) disposed on the first and second surfaces ( ) are electrically connected with at least one of the routing strips ( ), wire bonding ( ) electrically connecting at least one bonding pad ( ) to at least one of the routing strips ( ) and a silicon chip ( ) attached to the printed circuit board ( ) by an adhesive material ( ) that provide a seal between silicon chip ( ) and printed circuit board ( ) is disclosed.

Method for adhering and sealing a silicon chip in an integrated circuit package

Integrated circuit package

A high density unit (,) comprising a first integrated circuit package (,) comprising a carrier (,) having first and second sides (,), a silicon chip (,) attached by an adhesive layer (,) and solder bonding (,) electrically connecting the silicon chip (,) to the carrier (,) stackably and electrically connected to a second integrated circuit package (,), is disclosed.

Stacked double sided integrated circuit package

An integrated circuit package having a top opening and a cavity, with a chip adhered in the cavity. The top opening has routing strips electrically connecting the top opening with the outer surface. The routing strips are electronically connected to bonding pads located in a central area of the chip. Following assembly of the components, the top opening and the cavity are encapsulated in a molding process. A method is provided for forming a substantially flat integrated circuit package.

Integrated circuit package and flat plate molding process for integrated circuit package

A method and apparatus for producing an integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending into the opening (86), a plurality of pads (100) disposed on the first and second surfaces (92, 94) are electrically connected with at least one of the routing strips (82), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and a silicon chip (50) attached to the printed circuit board (70) by an adhesive material (60) that provide a seal between silicon chip (50) and printed circuit board (70) is disclosed.

Method for adhering and sealing a silicon chip in an integrated circuit

A double sided single inline memory module (20) comprising a substrate (70) having a plurality of openings (86) and first and second surfaces (92, 94), a plurality of pads (82) being integral with the substrate (70) and extending into the opening (86), a plurality of chips (50) adhered to the substrate (70) having bonding pads (120), wire bonding (80) electrically connecting at least one of the bonding pads (120) to at least one of the pads (82) and potting material (90) encapsulating the wire bonding (80) and filling the opening (86) is disclosed.

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Singapore, Singapore

Boon Pew Chan