Agere Systems Inc.

Lsi Corporation

Other

Lucent Technologies Inc.

Bonnie E Weir

Edward Belden Harris

Taeho Kook

Glenn B Alers

Tanya Nigam

Kathleen Susan Krisch

Ramnath Venkatraman

David Averill Bell

Kausar Banoo

A first MOS transistor has a channel length. Based on a parameter associated with the first MOS transistor, the first MOS transistor is selected to be simulated as at least a first transistor and a second transistor in series. The circuit is simulated with the first transistor and the second transistor in place of the first MOS transistor. Based on the results of the simulation, device degradations are calculated for the first transistor the second transistor. A degraded netlist is created. In the degraded netlist, the first transistor is degraded by a device degradation for the first transistor. The second transistor is degraded by a device degradation for the second transistor. The circuit is re-simulated with the first degraded transistor and the second degraded transistor in place of the first MOS transistor.

Breaking up long-channel field effect transistor into smaller segments for reliability modeling

A method for checking for reliability problems of an integrated circuit that includes determining a total MOS transistor gate area for an entire integrated circuit. Based on the total MOS transistor gate area, a time dependent dielectric breakdown lifetime (TDDB) is calculated.

Using entire area of chip in TDDB checking

An IC capacitor bank includes a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces. A fusible trace located on an end of one of the pair of conductive traces forms a capacitor column connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column. Additionally, a method of manufacturing an IC capacitor bank includes providing a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces and locating a fusible trace on an end of the pair of conductive traces to form a capacitor column that is connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column.

Mitigation of detrimental breakdown of a high dielectric constant metal-insulator-metal capacitor in a capacitor bank

The present invention, in one aspect, provides an integrated circuit that comprises a first region of transistors having gate structures with a low dopant concentration, and a second region of transistors having gate structures with a dopant concentration substantially higher than the gate structures of the first region, and wherein the transistors in the first region comprise a substantial portion of the integrated circuit. The transistors may include a resistor region located between an upper portion of the gate and the gate dielectric.

Semiconductor device and process for reducing damaging breakdown in gate dielectrics

A hot-carrier injection (HCI) test that permits rapid screening of integrated circuit wafers susceptible to possible HCI-induced failures is disclosed. A method is described that determines transistor stress voltages that results in a transistor HCI-induced post-stress drain current differing from a pre-stress drain current within a desired range. These stress voltages are determined using a wafer with acceptable HCI susceptibility. Additional wafers to be tested are first tested using a described method that uses the determined transistor stress voltages to quickly screen the wafers for HCI susceptibility and, if HCI susceptibility is found, then additional conventional HCI testing may be applied to the susceptible wafers.

Hot-electronic injection testing of transistors on a wafer

Reliability testing circuitry is built into the wafer or IC package in the form of one or more individual testers that use small-area transistors as DUTs. Stress can be applied to the DUTs in parallel and information about breakdown, wearout or failure can be obtained from the individual testers. Only a few pads are needed to test hundreds and even thousands of the DUTs of the individual testers. Testing of many DUTs may be performed using a simple power supply and a few probes.

Embedded test circuitry and a method for testing a semiconductor device for breakdown, wearout or failure

The breakdown of an ultra-thin dielectric layer is detected by applying a test signal to the layer. Measurements are taken of noise signals present in the layer during the application of the test signal. At breakdown, a significant increase occurs in the amplitude of the measured noise signals. Similarly, fluctuations in quiescent current, I.sub.DDQ, (I.sub.DDQ noise signals), rather than the values of I.sub.DDQ, are utilized during testing as the basis for detecting defects in integrated circuits.

Detecting defects in integrated circuits

The breakdown of an ultra-thin dielectric layer is detected by applying a test signal to the layer. Measurements are taken of noise signals present in the layer during the application of the test signal. At breakdown, a significant increase occurs in the amplitude of the measured noise signals.

Growing community of inventors

Bronxville, NY, United States of America

Bonnie E Weir