Samsung Electronics Co., Ltd.

Bongsoon Lim

Yonghyuk Choi

Jaeduk Yu

Sang-won Shim

Sangwon Park

Hongsoo Jeon

Sangwan Nam

Sang-Won Park

Sang-Wan Nam

Daeseok Byeon

Jung-Yun Yun

Ji-Suk Kim

Kang-Bin Lee

Jae-Duk Yu

Minsu Kim

Byungsoo Kim

Hyun-Wook Wook Park

Hyunggon Kim

Jooyong Park

Yoonhee Choi

Kuihan Ko

Changyeon Yu

Sangwon Shim

Seokmin Yoon

Sang-won Park

Jin-Young Kim

Chanho Kim

Yoon-Hee Choi

Heeseok Eun

Jinwook Lee

Pansuk Kwak

Sujeong Kim

Chaehoon Kim

Minjae Seo

Jeunghwan Park

Dongha Shin

Sun-Min Yun

Jeawon Jeong

Won-taeck Jung

Youse Kim

Wonbo Shim

Han Il Park

Heewon Son

Hojoon Kim

A semiconductor device may include stacks extended in a first direction on a substrate, separation structures extended in the first direction and respectively provided between the stacks, vertical channels penetrating each of the stacks, bit lines extended in a second direction crossing the first direction, each of the vertical channels being overlapped with a pair of the bit lines, and contact plugs connecting the bit lines to the vertical channels. Each of the stacks may include electrodes stacked on the substrate and at least two upper separation patterns dividing an upper one of the electrodes into several portions in the second direction. The vertical channels may be classified into a plurality of types, depending on a distance from one of the separation structures in the second direction, and each of the bit lines may be connected to all types of the vertical channels.

Semiconductor device and electronic system therewith

Disclosed is a memory system including a memory device and a memory controller. The memory device includes a package of a first memory chip configured to receive input/output signals through first input/output pads and a second memory chip having second input/output pads connected to the first input/output pads by a mapping connection. The memory controller configured to provide the input/output signals to the memory device. The second memory chip is configured to receive input/output signals different from the input/output signals provided by the memory controller to the first memory chip due to the mapping connection. The first and second memory chips are configured to selectively ignore the input/output signals provided by the memory controller based on the mapping connection.

Memory device reducing i/o signal lines through i/o mapping connection and memory system including the same

A memory device includes a first cell array region and a second cell array region separated by a separation region, each including at least one memory block having a plurality of gate electrode layers stacked in a first direction. The gate electrode layers include an upper select electrode layer including a plurality of string select lines, and a first electrode layer including a plurality of first word lines arranged below the string select lines. The first word lines include a first connection line to connect first end portions of the first word lines positioned on the opposite side of the separation region to each other and a plurality of second connection lines to connect some of second end portions of the plurality of first word lines adjacent to the separation region to each other, wherein each of the second connection lines is shorter than the first connection line.

Memory devices

A memory device includes a memory cell array, a reference generating circuit, a row decoding circuit that is connected to the memory cell array through word lines, a page buffer circuit that is connected to the memory cell array through bit lines, a data input/output circuit that is connected to the page buffer circuit through a data line, a buffer circuit, a control logic circuit that performs logic sequences, based on the internal clock signal and the internal power, and a test mode circuit. When the memory device enters a test mode, the test mode circuit disables a part of components of the reference generating circuit. In the test mode, the control logic circuit performs the logic sequences by using an external clock signal provided from an external device.

Memory device, operation method of memory device, and operation method of test device configured to test memory device

A nonvolatile memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes word-lines, bit-lines and a memory cell array which includes one or more memory blocks spaced apart from each other, one or more dummy blocks between the one or more memory blocks and a through-hole via region. The second semiconductor layer is under the first semiconductor layer includes a control circuit. The control circuit divides each of the one or more dummy blocks into an adjacent sub-block directly contacting the through-hole via region and a non-adjacent sub-block based on a relative distance from the through-hole via region in the first direction and uses each of the non-adjacent sub-blocks as a sub-block to store data.

Nonvolatile memory device

A method is provided to operate a storage device including a storage controller and a plurality of nonvolatile memory devices. A plurality of original data blocks are received at the storage controller from a host. An original parity block is generated based on the original data blocks. The original data blocks and the original parity block are stored in respective ones of the nonvolatile memory devices, wherein a first original data block of the original data blocks is stored in a first one of the nonvolatile memory devices, and wherein the original parity block is stored in a second one of the nonvolatile memory devices. A new data block corresponding to the first original data block is received at the storage controller from the host after storing the original data blocks and the original parity block. The new data block is stored in the first nonvolatile memory device. A new parity block is generated at the second nonvolatile memory device based on the original parity block and based on differences between the first original data block and the new data block.

Storage devices including nonvolatile memory and related methods of operating such storage devices

A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.

Memory devices having cell over periphery structure, memory packages including the same, and methods of manufacturing the same

A non-volatile memory device includes a plurality of word lines stacked above a substrate in a vertical direction; erase control lines that are spaced apart from each other in a first direction and extend in a second direction; a pass transistor circuit including a first pass transistor connected to a first group of erase control lines and a second pass transistor connected to a second group of erase control lines; and a memory cell array including a plurality of blocks. The first group of erase control lines are relatively close to a word line cut region and the second group of erase control lines are relatively far from the word line cut region. Each of the plurality of blocks includes a plurality of channel structures connected to the word lines and the erase control lines and each channel structure extends in the vertical direction.

Non-volatile memory device

Disclosed is a three-dimensional semiconductor device comprising channel regions that penetrate the stack structure and extend in a direction perpendicular to a top surface of the first substrate, a first interlayer dielectric layer on the stack structure, and a peripheral circuit structure on the first interlayer dielectric layer. The peripheral circuit structure includes peripheral circuit elements on a first surface of a second substrate. The peripheral circuit elements are electrically connected to the channel regions and at least one of the gate electrodes. The first substrate has a first crystal plane parallel to the top surface thereof. The second substrate has a second crystal plane parallel to the first surface thereof. An arrangement direction of atoms of the first crystal plane intersects an arrangement direction of atoms of the second crystal plane.

Three-dimensional semiconductor devices

A non-volatile memory device including a memory cell region over a peripheral circuit region. The memory cell region includes an upper substrate, channel structures extending in a vertical direction, and a first upper metal line extending in a first direction. The peripheral circuit region includes a first lower metal line extending in a second direction, and first and second via structures on the first lower metal line, a top surface of the second via structure in contact with the upper substrate. The memory cell region includes a first through-hole via structure passing through the upper substrate and the first via structure, and electrically connecting the first upper metal line to the first lower metal line; and the first upper metal line is electrically connected to the upper substrate through the first through-hole via structure, the first lower metal line, and the second via structure.

Non-volatile memory device including common source line tapping wire connected to common source line plate by vias on lower metal line and through-hole vias

A nonvolatile memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes word-lines, at least one string selection line, at least one ground selection line, and a memory cell array including at least one memory block. The second semiconductor includes a first address decoder and a second address decoder. The first address decoder is disposed under a first extension region adjacent to a first side of a cell region and includes a plurality of first pass transistors driving the word-lines, the at least one string selection line, and the at least one ground selection line. The second address decoder is disposed under a second extension region adjacent to a second side of the cell region and includes a plurality of second pass transistors driving the at least one string selection line and the at least one ground selection line.

Non-volatile memory device and method of operating nonvolatile memory device

A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.

Three-dimensional semiconductor memory device

A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells and a first peripheral circuit disposed below the first memory cell array; a second memory area including a second memory cell array having a plurality of second memory cells and a second peripheral circuit disposed below the second memory cell array; and a pad area including a power wiring. The first and second memory areas respectively include first and second local lockout circuits separately determining whether to lock out of each of the memory areas. The first and second memory areas are included in a single semiconductor chip to share the pad area, and the first and second memory areas operate individually. Accordingly, in the memory device, unnecessary data loss may be reduced by selectively stopping an operation of only a memory area requiring recovery.

Memory device

A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.

Memory system and method of operating the same

A vertical memory device includes a plurality of word lines on a substrate, a plurality of word line cut regions extending parallel to each other, a memory cell array comprising a plurality of channel structures extending on the substrate through the plurality of word lines and arranged in a honeycomb structure, a plurality of contacts on the plurality of channel structures, and a plurality of bit lines connected to the plurality of channel structures through the plurality of contacts. The memory cell array comprises a first sub-array and a second sub-array, which are defined by the plurality of word line cut regions and are connected to some identical bit lines from among the plurality of bit lines, and a layout of contacts in the first sub-array from among the plurality of contacts is different from a layout of contacts in the second sub-array from among the plurality of contacts.

Vertical memory device

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Seoul, South Korea

Bongsoon Lim