Samsung Electronics Co., Ltd.

Bongju Cho

Myungsam Kang

Youngchan Ko

Jeongseok Kim

Younggwan Ko

Kyungdon Mun

Yieok Kwon

Gongje Lee

Gun Goo Lee

Yongkoon Lee

Moonil Kim

Jaekul Lee

Kyung Don Mun

Changbae Lee

A semiconductor package includes: a first redistribution structure having a first surface and a second surface opposing the first surface, and including a first insulating layer and a first redistribution layer disposed on the first insulating layer; a semiconductor chip disposed on the first surface of the first redistribution structure, and including a connection pad electrically connected to the first redistribution layer and embedded in the first insulating layer; a vertical connection structure disposed on the first surface and electrically connected to the first redistribution layer; an encapsulant encapsulating at least a portion of each of the semiconductor chip and the vertical connection structure; a second redistribution structure disposed on the encapsulant and including a second redistribution layer electrically connected to the vertical connection structure; and a connection bump disposed on the second surface and electrically connected to the first redistribution layer.

Semiconductor package

A semiconductor package includes a lower redistribution structure including a wiring layer, and a via connected to the wiring layer; a semiconductor chip on the lower redistribution structure; wiring patterns disposed on the lower redistribution structure and extending in a horizontal direction, the wiring patterns including a first wiring pattern; metal patterns on the wiring patterns, the metal patterns including a first connection pillar and a first dummy pillar disposed on the first wiring pattern; an encapsulant on the lower redistribution structure, the semiconductor chip, the wiring patterns, and the metal patterns; and an upper redistribution structure on the encapsulant. The first connection pillar is directly connected to the upper redistribution structure.

Semiconductor packages having wiring patterns

A semiconductor package includes a redistribution substrate having a dielectric layer and a wiring pattern in the dielectric layer, the wiring pattern including a line part that extends horizontally, and a via part connected to the line part, the via part having a width less than a width of the line part, a passivation layer on a top surface of the redistribution substrate, the passivation layer including a material different from a material of the dielectric layer, a conductive pillar that penetrates the passivation layer, the conductive pillar being connected to the via part, and a connection terminal on a top surface of the conductive pillar, a distance between the top surface of the conductive pillar and a top surface of the passivation layer being greater than a thickness of the passivation layer.

A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip electrically connected to the first redistribution layer; a vertical connection structure adjacent a periphery of the semiconductor chip and electrically connected to the first redistribution layer; and an encapsulant on the vertical connection structure. The vertical connection structure includes a metal pillar having a bottom surface facing the redistribution substrate, a top surface positioned opposite to the bottom surface, and a side surface positioned between the bottom surface and the top surface. The vertical connection structure further includes a plating layer on each of the bottom surface, the top surface, and the side surface of the metal pillar, and having a roughened surface.

A semiconductor package includes: a redistribution substrate including a lower insulating layer, a redistribution via penetrating through the lower insulating layer, a redistribution layer connected to the redistribution via on the lower insulating layer, and an upper insulating layer on the lower insulating layer and having a first surface and a second surface opposing the first surface; a pad structure including a pad portion, disposed on the first surface of the redistribution substrate, and a via portion penetrating through the upper insulating layer to connect the redistribution layer and the pad portion to each other; a semiconductor chip disposed on the first surface of the redistribution substrate and including a pad; and a connection member in contact with the pad portion and the pad of the semiconductor chip between the pad structure and the pad of the semiconductor chip. The pad portion of the pad structure has a hemispherical shape, and a side surface of the via portion of the pad structure is in contact with the upper insulating layer.

A semiconductor package includes a first redistribution structure having a first surface in which a first pad and a second pad are embedded and including a first redistribution layer thereon, and a vertical connection structure including a land layer and a pillar layer. The land layer is embedded in the first surface of the first redistribution structure, and a width of an upper surface of the land layer is narrower than a width of a lower surface of the pillar layer.

A semiconductor package includes: a connection structure having a first surface and a second, and including a redistribution layer; a passive component disposed on the first surface of the connection structure, and electrically connected to the redistribution layer; a semiconductor chip disposed on the first surface of the connection structure, and electrically connected to the redistribution layer; a first encapsulant disposed on the first surface of the connection structure and covering at least a portion of the semiconductor chip; a second encapsulant disposed on the first surface of the connection structure and covering at least a portion of the passive component; an antenna substrate disposed on the first encapsulant and including a wiring layer, at least a portion of the wiring layer including an antenna pattern; and a through via penetrating at least a portion of each of the connection structure, the first encapsulant, and the antenna substrate.

A fan-out semiconductor package includes a first connection structure having first and second surfaces, a first semiconductor chip disposed on the first surface, a first encapsulant disposed on the first surface and covering at least a portion of the first semiconductor chip, a second semiconductor chip disposed on the second surface, one or more first metal members disposed on the second surface, one or more second metal members disposed on the second surface, a second encapsulant disposed on the second surface and respectively covering at least portions of the second semiconductor chip and the first and second metal members, and a second connection structure disposed on an opposite side of a side of the second encapsulant, on which the first connection structure is disposed.

Fan-out semiconductor package

A fan-out type semiconductor package includes: a frame including a cavity and a middle redistribution layer (RDL) structure at least partially surrounding the cavity; a semiconductor chip in the cavity; a lower RDL structure on the frame and electrically connected with the semiconductor chip and the middle RDL structure; an upper RDL structure on the frame and electrically connected with the middle RDL structure; an upper shielding pattern in the upper RDL structure to shield the semiconductor chip from electromagnetic interference (EMI); a lower shielding pattern in the lower RDL structure to shield the semiconductor chip from the EMI; and a side shielding pattern in the middle RDL structure to shield the semiconductor chip from the EMI. The upper shielding pattern and the lower shielding pattern have a thickness of no less than about 5 &#x3bc;m, and the side shielding pattern has a width of no less than about 5 &#x3bc;m.

Fan-out type semiconductor package

A semiconductor package includes a core member having a first surface and a second surface opposing each other, and an external side surface between the first and second surfaces, the core member having a through-hole connecting the first and second surfaces, having a protruding portion that protrudes from the external side surface, and having a surface roughness (Ra) of 0.5 &#x3bc;m or more, a redistribution substrate on the first surface of the core member, and including a redistribution layer; a semiconductor chip in the through-hole on the redistribution substrate, and having a contact pad electrically connected to the redistribution layer, and an encapsulant on the redistribution substrate, and covering the semiconductor chip and the core member, the protruding portion of the core member having a surface exposed to a side surface of the encapsulant.

Semiconductor package having core member and redistribution substrate

A semiconductor package includes: a connection structure including one or more redistribution layers; a core structure disposed on a surface of the connection structure; a semiconductor chip disposed on the surface and including connection pads electrically connected to the redistribution layers of the connection structure; a first encapsulant disposed on the surface and covering at least a portion of each of the core structure and the semiconductor chip; an antenna substrate disposed on the first encapsulant and including one or more wiring layers, at least a portion of the wiring layers including an antenna pattern; and a through via penetrating at least a portion of each of the connection structure, the core structure, the first encapsulant, and the antenna substrate.

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Suwon-si, South Korea

Bongju Cho