Globalfoundries Singapore Pte. Ltd.

Globalfoundries U.S. Inc.

Bong Woong Mun

Jeoung Mo Koo

Upinder Singh

Khon Cho

Juan Boon Tan

Wanbing Yi

Kun Liu

Jeffrey B Johnson

Huihua Jiang

The present disclosure relates to semiconductor structures and, more particularly, to devices with a three dimensional channel and methods of manufacture. The structure includes: a drift region within a semiconductor substrate; a shallow trench isolation structure within the drift region; and a gate structure within the shallow trench isolation structure and extending to an upper surface of the semiconductor substrate adjacent to the drift region.

Device with three dimensional channel

Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. The structure includes a semiconductor substrate, a body well in the semiconductor substrate, a source region in the body well, a drain well in the semiconductor substrate, a drain region in the drain well, and a gate electrode laterally positioned between the source region and the drain region. The drain well includes an edge adjacent to the body well, and the edge of the drain well has a spaced relationship with the body well.

Extended-drain metal-oxide-semiconductor devices with a gap between the drain and body wells

The present disclosure relates to semiconductor structures and, more particularly, to devices with a metal field plate extension and methods of manufacture. The structure includes: a gate structure over a semiconductor substrate; a drift region under the gate structure; a source region adjacent to the gate structure; a drain region in the drift region; a isolation structure within the drift region; and a contact extending from the source region and into the isolation structure within the drift region.

Device with metal field plate extension

Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming same. The structure comprises a semiconductor substrate including a trench, a source and a drain in the semiconductor substrate, a dielectric layer inside the trench, and a gate in the dielectric layer. The trench has a first sidewall and a second sidewall, the source is adjacent to the first sidewall of the trench, the drain is adjacent to the second sidewall of the trench, and the gate is laterally between the first sidewall of the trench and the second sidewall of the trench. The structure further comprises an air gap in the dielectric layer. The air gap is below the gate, and the air gap is laterally between the first sidewall of the trench and the second sidewall of the trench.

Laterally-diffused metal-oxide-semiconductor devices with an air gap

A device includes a first region disposed on a substrate, a second region disposed on the first region, a third region disposed in the second region and a first terminal region disposed in the third region. The first region comprises a discontinuous layer including at least one gap portion. The at least one gap portion comprises a portion of the substrate. The first region and the second region have a first conductivity type, and the substrate, the third region and the first terminal region have a second conductivity type. The first conductivity type is different from the second conductivity type.

Semiconductor device for high voltage applications

The embodiments herein relate to field-effect transistors (FETs) with a gate structure in a dual-depth trench isolation structure and methods of forming the same. The FET includes a substrate having an upper surface, a trench isolation structure, and a gate structure adjacent to the trench isolation structure. The trench isolation structure has a first portion having a lower surface and a second portion having a lower surface in the substrate; the lower surface of the first portion is above the lower surface of the second portion.

Field-effect transistors with a gate structure in a dual-depth trench isolation structure

A semiconductor device may include a substrate having a source region and a drain region, and a gate arranged over the substrate and between the source region and the drain region. A first interlevel dielectric (ILD) layer may be at least partially arranged over the substrate and the gate. A conductive field plate may be arranged over the first ILD layer. At least one drain contact may extend through the first ILD layer over the drain region and may be coupled to the conductive field plate. A drain captive structure may be disposed in the first ILD layer and adjacent to the drain region, the drain captive structure having a trench comprising an air gap, wherein the drain captive structure is laterally spaced apart from sidewalls of the gate.

Semiconductor devices including a drain captive structure having an air gap and methods of forming the same

Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. The structure includes a substrate, a source region and a drain region in the substrate, a buffer dielectric layer positioned on the substrate adjacent to the drain region, and a gate electrode laterally positioned between the source region and the drain region. The gate electrode includes a portion that overlaps with the buffer dielectric layer, and the portion of the gate electrode includes notches.

Extended-drain metal-oxide-semiconductor devices with a notched gate electrode

A structure includes a galvanic isolation including a horizontal portion including a first redistribution layer (RDL) electrode in a first insulator layer, and a second RDL electrode in the first insulator layer laterally spaced from the first RDL electrode. An isolation break includes a trench defined in the first insulator layer between the first RDL electrode and the second RDL electrode, and at least one second insulator layer in the trench. The first insulator layer and the second insulator layer(s) are between the first RDL electrode and the second RDL electrode. The isolation may separate, for example, voltage domains having different voltage levels. A related method is also disclosed. The isolation may also include a vertical portion using the first RDL electrode and another electrode in a metal layer separated from the first RDL electrode by a plurality of interconnect dielectric layers.

Galvanic isolation using isolation break between redistribution layer electrodes

The present disclosure generally relates to semiconductor structures for capacitive isolation, and structures incorporating the same. More particularly, the present disclosure relates to capacitive isolation structures for high voltage applications. The present disclosure also relates to methods of forming structures for capacitive isolation and the structures incorporating the same. The disclosed semiconductor structures may enable a smaller device footprint and reduced dimensions of components on an IC chip, whilst ensuring galvanic isolation between circuits.

Semiconductor structures for galvanic isolation

A semiconductor device is provided, which includes a multi-layered substrate, a first doped region, a second doped region, and a gate structure. The multi-layered substrate has a device layer over an isolation layer and the device layer includes a first region having a first substrate thickness and a second region having a second substrate thickness that is lesser than the first substrate thickness. The first doped region is in the first region and the second doped region is in the second region. The gate structure is between the first and second doped regions.

Semiconductor transistors on multi-layered substrates

A semiconductor device is provided, which includes a substrate, a first and second doped wells, a drain and source regions, a gate structure, a field plate and a booster plate. The first and second doped wells are arranged in the substrate. The drain region is arranged in the first doped well and the source region is arranged in the second doped well. The gate structure is arranged over the substrate and between the source and drain regions. The field plate is arranged over the first doped well and the booster plate arranged between the field plate and the first doped well.

Field-effect transistors of semiconductor devices

Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. First and second source/drain regions are formed in a substrate, and a gate electrode is formed over the substrate. The gate electrode has a sidewall, and the gate electrode is laterally positioned between the first source/drain region and the second source/drain region. A buffer dielectric layer is formed that includes a first dielectric layer having a first portion positioned between the substrate and the gate electrode. The dielectric layer also has a second portion positioned on the substrate laterally between the sidewall of the gate electrode and the first source/drain region. The first portion of the dielectric layer has a first thickness, and the second portion of the first dielectric layer has a second thickness that is less than the first thickness.

Extended-drain metal-oxide-semiconductor devices with a multiple-thickness buffer dielectric layer

A capacitor is provided. The capacitor includes a first conductive layer in a first isolation region in a substrate and a plurality of dielectric layers over the first isolation region. The plurality of dielectric layers may include inter layer dielectric (ILD) and inter metal dielectric (IMD) layers. The first conductive layer is a bottom plate of the capacitor. A second conductive layer is arranged over the plurality of dielectric layers, whereby the second conductive layer is a top plate of the capacitor and at least partially overlaps with the first conductive layer.

High voltage decoupling capacitor and integration methods

A nonvolatile memory device is provided. The nonvolatile memory device comprises a floating gate arranged over a first active region, whereby the first active region is in an active layer of a substrate. A metal-insulator-metal (MIM) capacitor may be provided laterally adjacent to the floating gate, whereby a portion of the metal-insulator-metal capacitor is in the active layer. A contact pillar may connect a first electrode of the metal-insulator-metal capacitor to the floating gate.

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Singapore, Singapore

Bong Woong Mun