Silicon Storage Technology, Inc.

International Business Machines Corporation

Microchip Technology Inc.

Other

Bomy A Chen

Dana Lee

Justin Sato

Jack Frayer

Sonu Daryanani

Sohrab Kianian

Kai Man Yue

Hieu Van Tran

Yaojian Leng

Ya-Fen Lin

Julius Kovats

Chung H Lam

Ramachandra Divakaruni

Bing Yeh

Subhash Balakrishna Kulkarni

Yaw Wen Hu

Mel Hymas

Edward J Nowak

Yuniarto Widjaja

Subramanian Srikanteswara Iyer

Herbert Lei Ho

Richard Stephan Wise

Hung Quoc Nguyen

Randy William Mann

Paul Christian Parries

Werner A Rausch

Nivo Rovedo

Hongwen Yan

Paul David Agnello

Francis Roger White

Zhitang Song

Dennis Sinitsky

Prateep Tuntasood

Scott W Crowder

Hsing-Jen C Wann

Feng Gao

Sychyi Fang

Wen-Juei Lu

Andrew Alexander Taylor

Robert Lutwak

Songlin Feng

Qiang Wu

Jay G Harrington

Elbert Lin

Jack Allan Mandelman

John Edward Cronin

Steven J Holmes

Oleg Gluschenkov

Kevin K Chan

Mark Charles Hakey

Charles W Koburger, Iii

Jed Hickory Rankin

Son Van Nguyen

Terence B Hook

Arne Watson Ballantine

Ying Di Zhang

Hariklia Deligianni

Douglas Duane Coolbaugh

John Michael Cotte

Laertis Economikos

Matthew Joseph Breitwisch

Hyun K Lee

Gary Bela Bronner

Rajarao Jammy

Christopher Joseph Waskiewicz

Amitay Levi

Jerome Brett Lasky

Douglas J Lee

Robert Hannon

Brian L Ji

Changyuan Chen

Siddhartha Panda

Jeng-Wei Yang

Rebecca D Mih

Hing Wong

Paul E Bakeman, Jr

Der-Tsyr Fan

Chun-Ming Chen

Kent D Hewitt

Scott Josef Bukofsky

John W Golz

Victor Ku

Ricky S Amos

Jin J Wu

James Walls

Isao Nojima

Chorng-Lii Hwang

Teresa Jacqueline Wu

Sundar Kumar Iyer

Pavel Klinger

Kevin M Houlihan

Liang-Kai Han

Heidi L Greer

Tsung-Lu Syu

Jeffrey A Shields

Gary L Patton

Dennis Hoyniak

Henry J Grabarz

Jack Wong

Greg Stom

An electronic device includes an integrated circuit package including a die mounted on a die carrier, a mold structure at least partially encapsulating the mounted die, and a heat transfer chimney formed on the die. The heat transfer chimney extends at least partially through the mold structure to transfer heat away from the die. The heat transfer chimney is formed from a thermally conductive compound including thermally conductive nanoparticles.

Integrated circuit package with heat transfer chimney including thermally conductive nanoparticles

Vapor cells may include a body including a cavity within the body. A first substrate bonded to a second substrate at an interface within the body, at least one of the first substrate, the second substrate, or an interfacial material between the first and second substrates may define at least one recess or pore in a surface. A smallest dimension of the at least one recess or pore may be about 500 microns or less, as measured in a direction parallel to at least one surface of the first substrate partially defining the cavity.

Vapor cells and related systems and methods

An integrated circuit device may include a multi-material toothed bond pad including (a) an array of vertically-extending teeth formed from a first material, e.g., aluminum, and (b) a fill material, e.g., silver, at least partially filling voids between the array of teeth. The teeth may be formed by depositing and etching aluminum or other suitable material, and the fill material may be deposited over the array of teeth and extending down into the voids between the teeth, and etched to expose top surfaces of the teeth. The array of teeth may collectively define an abrasive structure. The multi-material toothed bond pad may be bonded to another bond pad, e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad surfaces, to thereby create a direct and/or eutectic bonding between the bond pads.

Integrated circuit bond pad with multi-material toothed structure

An electronic device includes a first interposer, a first integrated circuit (IC) device affixed to the first interposer, a second interposer, and a second IC device affixed to the second interposer. he second interposer is bonded to the first interposer. The first interposer includes first interposer circuitry and a first connection element electrically connected to the first interposer circuitry. The second interposer includes second interposer circuitry and a second connection element electrically connected to the second interposer circuitry. The second connection element is bonded to the first connection element to define a connection element pair. The connection element pair provides an electrical connection between the first interposer circuitry and the second interposer circuitry.

Electronic device including interposers bonded to each other

An integrated circuit package module includes an integrated circuit package device including a contact element, and a bonding system formed on the integrated circuit package device. The bonding system includes a bonding system substrate and a bonding element formed in the bonding system substrate and conductively coupled to the contact element of the integrated circuit package device. The bonding element includes (a) a conduction component conductively connected to the contact element, the conduction component formed from a first metal having a first melting point, and (b) a bonding component formed from a second metal having a second melting point lower than the first melting point of the first metal.

Integrated circuit package module including a bonding system

An integrated circuit (IC) package product, e.g., system-on-chip (SoC) or system-in-package (SiP) product, may include at least one integrated inductor having a core magnetic field (B field) that extends parallel to the substrate major plane of at least one die or chiplet included in or mounted to the product, which may reduce the eddy currents within each die/chiplet substrate, and thereby reduce energy loss of the indictor. The IC package product may include a horizontally-extending IC package substrate, a horizontally-extending die mount base arranged on the IC package substrate, at least one die mounted to the die mount base in a vertical orientation, and an integrated inductor having a B field extending in a vertical direction parallel to the silicon substrate of each vertically-mounted die, thereby providing a reduced substrate loss in the integrated inductor, which provides an increased quality factor (Q) of the inductor.

Integrated circuit (IC) package with integrated inductor having core magnetic field (B field) extending parallel to substrate

An integrated circuit chip (die) may include a force mitigation system for reducing or mitigating under-pad stresses typically caused by wire bonding. The IC die may include wire bond pads and a force mitigation system formed below each wire bond pad. The force mitigation system may include a 'shock plate' (e.g., metal region), a sealing layer located above the shock plate, and a force mitigation layer including an array of sealed voids between the metal region and the sealing layer. The sealed voids in the force mitigation layer may be defined by forming openings in an oxide dielectric layer and forming a non-conformal sealing layer over the openings to define an array of sealed voids. The force mitigation system may mitigate stresses caused by a wire bond on each wire bond pad, which may reduce or eliminate wire-bond-related damage to semiconductor devices located in the under-pad regions of the die.

Integrated circuit (IC) device including a force mitigation system for reducing under-pad damage caused by wire bond

A mixed-orientation multi-die ('MOMD') integrated circuit package includes dies mounted in different physical orientations. An MOMD package includes both (a) one or more dies horizontally-mounted dies (HMDs) mounted horizontally to a horizontally-extending die mount base and (b) one or more vertically-mounted dies (VMDs) mounted vertically to the horizontally-extending die mount base. HMDs may include FPGAs or other high performance chips, while VMDs may include low performance chips and other physical structures such as heat dissipators, memory, high voltage/analog devices, sensors, or MEMS, for example. The die mount base of an MOMD package may include structures for aligning and mounting VMD(s), for example, VMD slots for receiving each mounted VMD, and VMD alignment structures that facilitate aligning and/or guiding a vertical mounting of each VMD to the die mount base. MOMD packages may provide a reduced lateral footprint and increased die integration per unit area, as compared with conventional multi-die packages.

Mixed-orientation multi-die integrated circuit package with at least one vertically-mounted die

A memory cell having a structure of a modified flash memory cell, but configured to operate in a low voltage domain (e.g., using voltages of &#x2264;6V amplitude for program and/or erase operations) is provided. The disclosed memory cells may be formed with dielectric layers having reduced thickness(es) as compared with conventional flash memory cells, which allows for such low voltage operation. The disclosed memory cells may be compatible with advanced, high density, low energy data computational applications. The disclosed memory cells may replace or reduce the need for RAM (e.g., SRAM or DRAM) in a conventional device, e.g., microcontroller or computer, and are thus referred to 'RAM Flash' memory cells. Data retention of RAM Flash memory cells may be increased (e.g., to days, months, or years) by (a) applying a static holding voltage at selected nodes of the cell, and/or (b) periodically refreshing data stored in RAM Flash.

Flash memory cell adapted for low voltage and/or non-volatile performance

A method for manufacturing a flash memory device on a substrate may include: preparing the substrate with shallow trench isolation to define active sections; depositing a floating gate oxide layer on the prepared substrate; depositing a floating gate polysilicon layer on the floating gate oxide layer; polishing the floating gate polysilicon layer to isolate a plurality of floating gates above the active sections of the substrate; depositing a silicon nitride layer on top of the plurality of floating gates; patterning and etching the silicon nitride layer to create silicon nitride features; depositing a set of oxide spacers along sides of the silicon nitride features; implanting a source junction into the substrate beneath the individual floating gates; removing the floating gate polysilicon layer except where beneath individual oxide spacers, then removing the set of oxide spacers; depositing an inter-poly layer on top of the remaining floating gates; depositing a second polysilicon layer on top of the inter-poly layer; and patterning and etching the second polysilicon layer to separate the second polysilicon layer into word line devices and erase gates.

Non-volatile flash memory cell

A method of forming a memory cell, e.g., flash memory cell, may include (a) depositing polysilicon over a substrate, (b) depositing a mask over the polysilicon, (c) etching an opening in the mask to expose a surface of the polysilicon, (d) growing a floating gate oxide at the exposed polysilicon surface, (e) depositing additional oxide above the floating gate oxide, such that the floating gate oxide and additional oxide collectively define an oxide cap, (f) removing mask material adjacent the oxide cap, (g) etching away portions of the polysilicon uncovered by the oxide cap, wherein a remaining portion of the polysilicon defines a floating gate, and (h) depositing a spacer layer over the oxide cap and floating gate. The spacer layer may includes a shielding region aligned over at least one upwardly-pointing tip region of the floating gate, which helps protect such tip region(s) from a subsequent source implant process.

Memory cell with oxide cap and spacer layer for protecting a floating gate from a source implant

A method of bonding a first substrate to a second substrate, wherein the first substrate includes first electrical contacts on a top surface of the first substrate, and wherein the second substrate includes second electrical contacts on a bottom surface of the second substrate. The method includes forming a block of polyimide on the top surface of the first substrate, wherein the block of polyimide has a rounded upper corner, and vertically moving the top surface of the first substrate and the bottom surface of the second substrate toward each other until the first electrical contacts abut the second electrical contacts, wherein during the moving, the second substrate makes contact with the rounded upper corner of the polyimide causing the first and second substrates to move laterally relative to each other.

Sacrificial alignment ring and self-soldering vias for wafer bonding

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Ridgefield, CT, United States of America

Bomy A Chen