Skhynix Inc.

Hynix Semiconductor Inc.

Bok Gyu Min

Da Un Nah

Sukwon Lee

Tae Yong Lee

Ki Bum Kim

Jae Myun Kim

Suk Won Lee

Jong Hyun Kim

Qwan Ho Chung

Jin Ho Bae

So Hyun Jung

Jae Joon Ahn

Kyoung Sook Park

Jung Tae Jeong

Joon Ki Hong

Seong Kweon Ha

Jae Won Shin

A semiconductor package may include a first die disposed on a package substrate, a second die stacked on the first die, and a first position checker disposed on the package substrate. The first position checker may indicate a first position allowable range in which a first side of the first die can be located.

Semiconductor packages including at least one die position checker

A semiconductor substrate including an upper surface and a lower surface may include a bump pad unit disposed on the upper surface. The semiconductor substrate may also include test pads disposed on the upper surface or the lower surface. The semiconductor substrate may also include traces configured to connect the bump pad unit and the test pads. The bump pad unit includes a main bump pad disposed on the upper surface, and a plurality of side bump pads disposed on the upper surface to be spaced apart from the main bump pad. The traces may connect the main bump pad and the plurality of side bump pads to the test pads in a one-to-one manner.

Semiconductor substrate, semiconductor package including semiconductor substrate, and test method of semiconductor substrate

A semiconductor package includes a package substrate including a die attachment region, a semiconductor die attached to the die attachment region, and a die over-shift indicating pattern disposed on or in the package substrate and spaced apart from the die attachment region. The die over-shift indicating pattern is used as a reference pattern for obtaining a shifted distance of the semiconductor die.

Semiconductor packages including die over-shift indicating patterns

A semiconductor package may include a package substrate to which a first semiconductor chip is attached, an encapsulant covering the first semiconductor chip, and an indicator disposed within the semiconductor package. A side surface of the indicator is exposed at a side surface of the semiconductor package, and a width of a vertical section of the indicator parallel with the exposed side surface of the indicator varies as the vertical section of the indicator becomes farther from the side surface of the semiconductor package.

Semiconductor packages including indicators for evaluating a distance and methods of calculating the distance

A method of manufacturing a semiconductor package includes: forming a strip substrate including a plurality of unit substrates, each being provided with a first connection pad and a second connection pad on a first surface of the unit substrate and each unit substrate being electrically and physically isolated from each other with the intervention of saw lines, first ground connection pads formed on the respective unit substrates, each of the first ground connection pads being electrically coupled with the first connection pad over the respective unit substrates, second ground connection pads formed on the saw line on the first surface side of the unit substrates and electrically isolated from the unit substrates, and test wiring formed on the saw line, the test wiring being electrically isolated from the unit substrates and electrically coupled with the second ground connection pads; and attaching semiconductor chips onto the respective unit substrates.

Semiconductor package and method for manufacturing the same

Semiconductor packages are provided. The semiconductor package includes a first chip having a first inclined sidewall in an edge of the first chip; and a second chip having a second inclined sidewall in an edge of the second chip and the second chip being horizontally adjacent to the first chip such that the first and second inclined sidewalls are in substantial contact with each other.

Semiconductor packages having the first and second chip inclined sidewalls contact with each other

A semiconductor package includes: first, second, third and fourth semiconductor chips stacked while having the arrangement of chip selection vias; and a connection unit provided between a second semiconductor chip and a third semiconductor chip, and configured to mutually connect some of the chip selection vias of the second and third semiconductor chips and disconnect the others of the chip selection vias of the second and third semiconductor chips, wherein the first and second semiconductor chips and the third and fourth semiconductor chips are stacked in a flip chip type.

Semiconductor package for selecting semiconductor chip from a chip stack

A stacked semiconductor package includes first and second semiconductor chips including semiconductor chip bodies which have circuit units, first through-electrodes which pass through the semiconductor chip bodies at first positions, and second through-electrodes which pass through the semiconductor chip bodies at second positions and provide a chip enable signal to the circuit units. A spacer including a spacer body may be interposed between the first semiconductor chip and the second semiconductor chip, with an inverter chip embedded in the spacer body. Wiring patterns formed on the spacer body may connect the first through-electrodes of the first semiconductor chip with the second through-electrodes of the second semiconductor chip, the first through-electrodes of the first semiconductor chip with input terminals of the inverter chip, and output terminals of the inverter chip with the second through-electrodes of the first semiconductor chip.

Selecting chips within a stacked semiconductor package using through-electrodes

A spiral staircase shaped stacked semiconductor package is presented. The package includes a semiconductor chip module, a substrate and connection members. The semiconductor chip module includes at least two semiconductor chips which have chip selection pads and through-electrodes. The semiconductor chips are stacked such that the chip selection pads are exposed and the through-electrodes of the stacked semiconductor chips are electrically connected to one another. The substrate has the semiconductor chip module mounted thereto and has connection pads. The connection members electrically connect the chip selection pads to respective connection pads.

Spiral staircase shaped stacked semiconductor package and method for manufacturing the same

A semiconductor package includes a semiconductor chip possessing a shape with corners and has a circuit section. The semiconductor chip has one or more chamfered portions which are formed in a first corner group that includes one or more of the corners. Data bonding pads are disposed on the semiconductor chip and are electrically connected to the circuit section. A chip selection pad is disposed adjacent to a second corner group that includes at least one of the corners which is not formed with a chamfered portion. The chip selection pad is electrically connected to the circuit section. A plurality of the semiconductor packages may be stacked so that the chip selection pad of one of the semiconductor packages is left exposed when another semiconductor package is stacked thereover due to the chamfered portion of the other semiconductor package.

Growing community of inventors

Icheon-si, South Korea

Bok Gyu Min