Intel Corporation

Bok Eng Cheah

Jackson Chung Peng Kong

Kooi Chi Ooi

Jenny Shio Yin Ong

Seok Ling Lim

Min Suet Lim

Khang Choong Yong

Shanggar Periaman

Howe Yin Loo

Ping Ping Ooi

Eng Huat Goh

Yen Hsiang Chew

Chin Lee Kuan

Poh Tat Oh

Tin Poay Chuah

Choong Kooi Chee

Wai Ling Lee

Tat Hin Tan

Howard L Heck

Yang Liang Poh

Stephen H Hall

Boon Ping Koh

Mooi Ling Chang

Wen Wei Lum

Michael P Skinner

Yun Rou Lim

Stephen H Hall, Jr

Loke Yip Foo

Teong Guan Yew

Nitesh Nimkar

Chan Kim Lee

Paik Wen Ong

Chung Peng Jackson Kong

Hungying Louis Lo

Toong Erh Ooi

David W Browning

Jiun Hann Sir

Kuan-Yu Chen

Wil Choon Song

Yong She

Amit Kumar Jain

Chaitanya Sreerama

Yun Ling

Sameer Shekhar

Ramaswamy Parthasarathy

Jiamiao Tang

Junfeng Zhao

Ranjul Balakrishnan

Su Sin Florence Phun

Khai Ern See

Chee Chun Yee

Mark A Schaecher

Han Kung Chua

Min Keen Tang

Teong Keat Beh

Saravanan Sethuraman

Chia Chuan Wu

Yee Lun Ong

Choy Mei Yeow

Lee Fueng Yap

Greg A La Tour

Chow Soon Lim

Kok Keng Wan

Yean Ling Soon

Kin Wai Lee

Ling Li Ong

Chia Voon Tan

Jackson Kong

Eric C Gantner

Ridza Effendi Abd Razak

Kheng Tat Mar

J-Wing Teh

Kok Hou Teh

Po Yin Yaw

The present disclosure relates to an electronic assembly including a package substrate with a first surface and an opposing second surface; a first interconnect disposed in the package substrate and extending between the first and the second surfaces; and a second interconnect disposed in the package substrate and extending between the first and the second surfaces; wherein the first interconnect comprises a first recessed side wall and the second interconnect is arranged adjacent the first recessed side wall.

Recessed vertical interconnects for device miniaturization

The present disclosure relates to a printed circuit board assembly including a first circuit board including a first footprint, the first circuit board further includes a plurality of first vertical vias extending between a first side and an opposing second side; a second circuit board including a second footprint smaller than the first footprint, the second circuit board further includes a plurality of second vertical vias extending between a subsequent first side and an opposing subsequent second side; an adhesive layer coupling the first side to the subsequent first side; and a plurality of third vertical vias extending through the first side and the subsequent first side.

Asymmetrical laminated circuit boards for improved electrical performance

According to various examples, a device is described. The device may include a first package substrate. The device may also include a first mold layer with a first thickness. The device may also include a second mold layer with a second thickness proximal to the first mold layer. The second thickness may be larger than the first thickness. The first mold layer may include a plurality of first interconnects coupled to the first package substrate. The second mold layer may include a plurality of second interconnects configured to couple the first package substrate to a printed circuit board.

Semiconductor package with hybrid mold layers

The present disclosure is directed to a hybrid dielectric interconnect stack for a printed circuit board having a first dielectric layer with a first dielectric constant and a first dielectric loss tangent positioned over an intermediate layer, which includes a first dielectric sublayer with a first sublayer dielectric constant and a first sublayer dielectric loss tangent, an embedded conductive layer, and a second dielectric sublayer with a second sublayer dielectric constant and a second sublayer dielectric loss tangent, in which the embedded conductive layer is positioned between the first and second dielectric sublayers, and a second dielectric layer with a second dielectric constant and a second dielectric loss tangent, in which the intermediate layer is positioned between the first and second dielectric layers.

Hybrid boards with embedded planes

Disclosed embodiments include silicon interconnect bridges that are in a molded frame, where the molded frame includes passive devices and the silicon interconnect bridge includes through-silicon vias that couple to a redistribution layer on both the silicon interconnect bridge and the molded frame.

Molded silicon interconnects in bridges for integrated-circuit packages

The present disclosure is directed to semiconductor packages, and methods for making them, which includes a substrate with a top surface and a bottom surface, a substrate recess in the bottom surface of the substrate, a first device positioned over the top surface of the substrate, which has the first device at least partially overlapping the substrate recess, a mold material in the substrate recess, which has the mold material overlapping the bottom surface of the substrate adjacent to the substrate recess, a second device positioned in the substrate recess, and a plurality of interconnect vias in the substrate, which has at least one of the plurality interconnect vias coupled to the first and second devices to provide a direct signal connection therebetween that minimizes signal latency.

Multi-chip package with recessed memory

Disclosed embodiments include molded interconnect bridges that are in a molded frame, where the molded frame includes passive devices that couple to a metal buildup layer that includes at least one power rail and one ground rail. The molded interconnects bridge is embedded in an integrated-circuit package substrate between a die side and a land side, and closer to the die side.

Molded interconnects in bridges for integrated-circuit packages

Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.

Composite bridge die-to-die interconnects for integrated-circuit packages

An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

Micro through-silicon via for transistor density scaling

A substrate may be included in an electronic device. The substrate may include a first layer that may include a dielectric material. The first layer may define a substrate surface. The substrate may include a second layer optionally including the dielectric material. The second layer may be coupled to the first layer. A wiring trace may be located in the substrate. A recess may extend through the substrate surface, the first layer, and may extend through the second layer. A substrate interconnect may be located within the recess. The substrate interconnect may be at least partially located below the substrate surface. The substrate interconnect may be in electrical communication with the wiring trace.

Electronic device and crosstalk mitigating substrate

An electronic device and associated methods are disclosed. In one example, the electronic device can include a semiconductor package including a package substrate, a first semiconductor die on the package substrate, a second semiconductor die on the package substrate, a third semiconductor die on the package substrate, and a bridge interconnect at least partially embedded in the package substrate. The bridge interconnect can include a first bridge section coupling the first semiconductor die to the second semiconductor die, a second bridge section coupling the second semiconductor die to the third semiconductor die, and a power-ground section between the first section and the second section, the power-ground section comprising first and second conductive traces coupled to the second semiconductor die.

Integrated bridge for die-to-die interconnects

Semiconductor packages, and methods for making the semiconductor packages, having an interposer structure with one or more interposer and an extension platform, which has an opening for placing the interposer, and the space between the interposer and the extension platform is filled with a polymeric material to form a unitary interposer-extension platform composite structure. A stacked structure may be formed by at least a first semiconductor chip coupled to the interposer and at least a second semiconductor chip coupled to the extension platform, and at least one bridge extending over the space that electrically couples the extension platform and the interposer. The extension platform may include a recess step section that may accommodate a plurality of passive devices to reduced power delivery inductance loop for the high-density 2.5D and 3D stacked packaging applications.

Interposer structures and methods for 2.5D and 3D packaging

To address the issue of shrinking volume that can be allocated for electrical components, a system can use an interposer with a flexible portion. A first portion of the interposer can electrically connect to a top side of a motherboard. A flexible portion of the interposer, adjacent to the first portion, can wrap around an edge of the motherboard. A peripheral portion of the interposer, adjacent to the flexible portion, can electrically connect to a bottom side of the motherboard. The peripheral portion can be flexible or rigid. The interposer can define a cavity that extends through the first portion of the interposer. A chip package can electrically connect to the first portion of the interposer. The chip package can be coupled to at least one electrical component that extends into the cavity when the chip package is connected to the interposer.

Interposer with flexible portion

A semiconductor package substrate includes an encapsulated interconnect on a land side of the substrate. The encapsulated interconnect includes an integral metallic structure that has a smaller contact end against the semiconductor package substrate, and a larger contact end for board mounting.

Encapsulated vertical interconnects for high-speed applications and methods of assembling same

Growing community of inventors

Bukit Gambir, Malaysia

Bok Eng Cheah