Taiwan Semiconductor Manufacturing Comp. Ltd.

Boh-Yi Huang

Chih-yuan Stephen Yu

Chao-Chun Lo

Yi-Lin Chuang

Chih-Sheng Hou

Xiang Guo

Tze-Chiang Huang

Brent Lui

Chen-jih Lui

Wenyuan Lee

Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.

Circuit synthesis optimization for implements on integrated circuit

Methods, systems, and computer program products are described for generating synthesizable netlists from register transfer level (RTL) designs to aid with semiconductor device design. These netlists provide RTL design information corresponding to a portion of a semiconductor device. A configuration tracer generates behavior information associated with the RTL design. A register compiler compiles a set of semiconductor devices based on one or more technologies and power, performance, and area (PPA) information related to the semiconductor device. Semiconductor devices generated by the register compiler that meet predefined power, performance, and area conditions are identified. Structural information for aligning the input/output ports of the semiconductor device is generated. A set of one or more synthesizable semiconductor device configurations is created based on user defined parameters such that one of the synthesizable semiconductor device designs may by selected to generate a design netlist with structure-synthesizable input/output boundary compatible semiconductor device modules.

Systems and methods for generating synthesizable netlists from register transfer level designs

A method and system for migrating an existing ASIC design from one semiconductor fabrication process to another are disclosed herein. In some embodiments, a method for migrating the existing ASIC design comprises parsing the gate-level netlist one row at a time into one or more standard cells forming the ASIC design, forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells into equivalent target standard cells implemented in the second semiconductor fabrication process, mapping the parsed one or more standard cells into the equivalent target standard cells using the plurality of mapping tables, and generating a target gate-level netlist describing the ASIC design in terms of the equivalent target standard cells.

Apparatus and method for mapping foundational components during design porting from one process technology to another process technology

Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA). The attribute mismatch is provided for further design or timing constraint modifications and/or updates using this approach, particularly timing formal verification, at the target technology in order to enable efficient design timing sign-off based on ported netlists and synthesis design constraints (SDC).

Attribute-point-based timing constraint formal verification

A method includes providing a register transfer level (RTL) description of a circuit design, providing a plurality of RTL-to-gate-level mapping details by translating the RTL description into a gate-level netlist, providing one or more input/output (I/O) variables as stimulus to simulate the RTL description of the circuit design, capturing a plurality of internal operation values from the simulated RTL description at a beginning time of a specified period of time wherein the specified period of time is less than a time period required to compete a full-scale simulation, mapping the captured internal operation values to corresponding gate-level nodes of the gate-level netlist, capturing a plurality of I/O values from the I/O variables at the beginning time of the specified period of time, and simulating the circuit design in a gate-level for the specified period of time based on the mapped internal operation values and the captured I/O values.

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San Jose, CA, United States of America

Boh-Yi Huang