Taiwan Semiconductor Manufacturing Comp. Ltd.

Bo-Jiun Lin

Tien-I Bao

Hai-Ching Chen

Ching-Yu Chang

Tung-Ying Lee

Tung Ying Lee

Yu-Chao Lin

Chen-Hua Douglas Yu

Yu Chao Lin

Hsin-Chieh Yao

Ching-Yu Lo

Shau-Lin Shue

Chung-Ju Lee

Shao-Ming Yu

Cheng-Hsiung Tsai

Hsien-Chang Wu

A semiconductor structure includes a substrate and an interconnect. The substrate has a semiconductor device. The interconnect is disposed over the substrate and electrically coupled to the semiconductor device, and includes a metallization layer and a capping layer. The metallization layer is disposed over the substrate and includes a via portion and a line portion connecting to the via portion. The capping layer covers the line portion, where the line portion is sandwiched between the via portion and the capping layer, and the capping layer includes a plurality of sub-layers.

Semiconductor structure and manufacturing methods thereof

The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.

System and method of forming a porous low-k structure

A device includes a substrate, a dielectric layer over the substrate, and a conductive interconnect in the dielectric layer. The conductive interconnect includes a barrier/adhesion layer and a conductive layer over the barrier/adhesion layer. The barrier/adhesion layer includes a material having a chemical formula MX, with M being a transition metal element, X being a chalcogen element, and n being between 0.5 and 2.

Interconnect structure of semiconductor device and method of forming same

Provided is an interconnect structure including: a first conductive feature, disposed in a first dielectric layer; a second conductive feature, disposed over the first conductive feature and the first dielectric layer; a via, disposed between the first and second conductive features and being in direct contact with the first and second conductive features; and a barrier structure, lining a sidewall and a portion of a bottom surface of the second conductive feature, a sidewall of the via, a portion of a top surface of the first conductive feature, and a top surface of the first dielectric layer.

Interconnect structure and semiconductor device having the same

An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.

Interconnect structure and method

A device includes a substrate; a first layer over the substrate, the first layer containing a plurality of fin features and a trench between two adjacent fin features. The device also includes a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C.

Porogen bonded gap filling material in semiconductor manufacturing

A memory cell includes a memory device, a connecting structure, an insulating layer and a selector. The connecting structure is disposed on and electrically connected to the memory device. The insulating layer covers the memory device and the connecting structure. The selector is located on and electrically connected to the memory device, where the selector is disposed on the insulating layer and connected to the connecting structure by penetrating through the insulating layer.

Semiconductor device, memory cell and method of forming the same

Provided is a method of forming an interconnect structure including: forming a via; forming a first barrier layer to at least cover a top surface and a sidewall of the via; forming a first dielectric layer on the first barrier layer; performing a planarization process to remove a portion of the first dielectric layer and a portion of the first barrier layer, thereby exposing the top surface of the via; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer has an opening exposing the top surface of the via; forming a blocking layer on the top surface of the via; forming a second barrier layer on the second dielectric layer; removing the blocking layer to expose the top surface of the via; and forming a conductive feature in the opening, wherein the conductive feature is in contact with the top surface of the via.

Method of forming interconnect structure

A device includes a substrate; a first layer over the substrate, the first layer containing a metallic material, wherein the first layer includes a trench; and a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C.

System and method of forming a porous low-K structure

Semiconductor device having a porous low-k structure

A method for semiconductor manufacturing includes receiving a device that includes a substrate and a first layer disposed over the substrate, wherein the first layer includes a trench. The method further includes applying a first material over the first layer and filling in the trench, wherein the first material contains a matrix and a porogen that is chemically bonded with the matrix. The method further includes curing the first material to form a porous material layer. The porous material layer has a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed over the first layer. The first and second portions contain substantially the same percentage of each of Si, O, and C. The first and second portions contain substantially the same level of porosity.

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Jhubei, Taiwan

Bo-Jiun Lin