Nvidia Corporation

Bo Hong

Emmett Michael Kilgariff

Michael J M Toksvig

Alexander Lev Minkin

Karim Abdalla

Joel James McCormack

Paul S Heckbert

John W Berendsen

Luke Y Chang

Walter E Donovan

Walter Donavan

Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.

Reconfigurable high-performance texture pipeline with advanced filtering

Reconfigurable high performance texture pipeline with advanced filtering

Growing community of inventors

Fremont, CA, United States of America

Bo Hong