Globalfoundries Inc.

International Business Machines Corporation

Globalfoundries U.S. Inc.

Bo Bai

Judson Robert Holt

Viorel C Ontalus

Kathryn Turner Schonenberg

Abhishek Dube

Keith Howard Tabakman

Ran Yan

Linda R Black

Matthew W Stoker

Ming-Cheng Chang

Bin Yang

Alban Zaka

El Mehdi Bazizi

Gabriela Dilliway

Qiang Lei

Structures for a corner area of a chip and methods of fabricating a structure for a corner area of a chip. A chip includes an active circuit region, an integrated circuit in the active circuit region, and a corner area. The corner area includes dummy structures that provide dummy fill.

Chip corner areas with a dummy fill pattern

A method of manufacturing a semiconductor device includes providing a semiconductor layer, forming a plurality of semiconductor fins on a surface of the semiconductor layer extending in parallel to each other along a first direction parallel to the surface of the semiconductor layer, and forming a plurality of gate electrodes comprising longitudinal portions extending parallel to the semiconductor fins along the first direction.

FinFET device with enlarged channel regions

A semiconductor device including a semiconductor layer, a plurality of semiconductor fins formed on a surface of the semiconductor layer and a plurality of gate electrodes formed over the surface of the semiconductor layer is provided. The semiconductor fins extend in parallel to each other along a first direction parallel to the surface of the semiconductor layer and have a first height in a second direction that is perpendicular to the first direction, and the gate electrodes comprise longitudinal portions extending parallel to the semiconductor fins along the first direction and, in particular, having a second height in the second direction lower than the first height.

In sophisticated semiconductor devices, transistors may be formed on the basis of an efficient strain-inducing mechanism by using an embedded strain-inducing semiconductor alloy. The strain-inducing semiconductor material may be provided as a graded material with a smooth strain transfer into the neighboring channel region in order to reduce the number of lattice defects and provide enhanced strain conditions, which in turn directly translate into superior transistor performance. The superior architecture of the graded strain-inducing semiconductor material may be accomplished by selecting appropriate process parameters during the selective epitaxial growth process without contributing to additional process complexity.

Performance enhancement in transistors by providing a graded embedded strain-inducing semiconductor region with adapted angles with respect to the substrate surface

A complementary metal oxide semiconductor (CMOS) circuit incorporating a substrate and a gate wire over the substrate. The substrate comprises an n-type field effect transistor (n-FET) region, a p-type field effect transistor (p-FET) region and an isolation region disposed between the n-FET and p-FET regions. The gate wire comprises an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate. A first conformal insulator covers the gate wire and a second conformal insulator is on the first conformal insulator positioned over the p-FET gate without extending laterally over the n-FET gate. Straining regions for producing different types of strain are formed in recess etched into the n-FET and p-FET regions of the substrate.

Method for growing strain-inducing materials in CMOS circuits in a gate first flow

A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and growing silicon carbon (SiC) in the exposed recesses.

An NMOS transistor is formed with improved manufacturability. An embodiment includes forming N-type doped embedded silicon germanium containing carbon (eSiGe:C) in source/drain regions of a substrate, and amorphizing the eSiGe:C. The use of eSiGe:C provides a reduction in extension silicon and dopant loss, improved morphology, increased wafer throughput, improved short channel control, and reduced silicide to source/drain contact resistance.

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Dresden, Germany

Bo Bai