Telefonaktiebolaget Lm Ericsson (publ)

Bo Anders Lindgren

Hans Erik Norstrom

Sam-Hyo Hong

Torbjorn Larsson

The present invention relates to a collector pin and a trench in an integrated circuit intended for high speed communication, and to a manufacturing method for these items. The collector pin is achieved by creating an area which is implantation damaged or made amorphous and at least partially doped ( ) by means of ion implantation from an upper silicon surface comprised in a semiconductor structure ( ) down to a depth lower than the depth of the surrounding field oxide ( ), and that the semiconductor structure ( ) is then heat treated. The trench ( ) is achieved by uncovering a predetermined area of the upper silicon surface ( ), etching the semiconductor structure ( ) within the predetermined area to a predetermined depth, uniformly depositing a first oxide layer ( ), preferably of the type LPCVD-TEOS over the semiconductor structure, especially in the trench, uniformly depositing a barrier layer ( ), preferably of silicon nitride, over the first oxide layer ( ), filling the trench ( ) by depositing a silicon layer ( ), which is subsequently etched back, over the nitride layer ( ), especially in the trench ( ), and thermally growing a cap oxide ( ) over the trench filling ( ).

Integrated circuit components thereof and manufacturing method

Integrated circuit, components thereof and manufacturing method

The present invention relates to a collector pin and a trench in an integrated circuit intended for high speed communication, and to a manufacturing method for these items. The collector pin is achieved by creating an area which is implantation damaged or made amorphous and at least partially doped (,) by means of ion implantation from an upper silicon surface comprised in a semiconductor structure (,) down to a depth lower than the depth of the surrounding field oxide (,), and that the semiconductor structure (,) is then heat treated. The trench (,) is achieved by uncovering a predetermined area of the upper silicon surface (,), etching the semiconductor structure (,) within the predetermined area to a predetermined depth, uniformly depositing a first oxide layer (,), preferably of the type LPCVD-TEOS over the semiconductor structure, especially in the trench, uniformly depositing a barrier layer (,), preferably of silicon nitride, over the first oxide layer (,), filling the trench (,) by depositing a silicon layer (,), which is subsequently etched back, over the nitride layer (,), especially in the trench (,), and thermally growing a cap oxide (,) over the trench filling (,).

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Sollentuna, Sweden

Bo Anders Lindgren