Changxin Memory Technologies, Inc.

Bingyu Zhu

Jingwen Lu

Zhaopei Cui

Wei Feng

Hai-Han Hung

Yin-kuei Yu

Shijie Bai

Haihan Hung

Embodiments disclose a buried bit line structure, a method for fabricating the buried bit line structure, and a memory. The buried bit line structure includes: a substrate having a bit line trench; a bit line metal filled in the bit line trench; and a bit line contact filled in the bit line trench and positioned on the bit line metal, where an arc-shaped contact surface is provided between the bit line contact and the bit line metal. By setting a contact surface between the bit line contact and the bit line metal to be the arc-shaped contact surface, a contact area between the bit line contact and the bit line metal is increased, electrical conductivity of the bit line structure is enhanced.

Buried bit line structure, method for fabricating buried bit line structure, and memory

The present disclosure relates to a method for manufacturing a semiconductor structure, the method includes: a substrate is provided; a bit line array is formed on an upper surface of the substrate, the bit line array includes several bit lines arranged at intervals, the bit lines are connected through at least one support pattern, and the at least one support pattern penetrates through the bit line array along an arrangement direction of the bit lines; a bit line side wall is formed on side walls of each of the bit lines; a part of the at least one support pattern is removed so as to expose at least one sacrificial layer; and the at least one sacrificial layer is removed, so as to form at least one air gap between the first side wall dielectric layers and the second side wall dielectric layers.

Semiconductor structure and method for manufacturing semiconductor structure

A forming method of a semiconductor structure includes the following: providing a semiconductor substrate formed with a first mask layer having a preset pattern; forming a second mask layer having a first mask pattern on a surface of the first mask layer, wherein the first mask pattern includes a plurality of first sub-patterns arranged in sequence; forming a second mask pattern in the second mask layer through the first mask pattern in a self-alignment manner, wherein the second mask pattern includes the first sub-patterns of the first mask pattern and second sub-patterns corresponding to the first sub-patterns; etching the first mask layer based on the first sub-patterns and the second sub-patterns of the second mask pattern to convert the preset pattern into an active area pattern; and defining active areas in the semiconductor substrate based on the active area pattern.

Semiconductor structure and forming method thereof

The present disclosure provides a method of manufacturing a buried bit line structure and a buried bit line structure. The method of manufacturing a buried bit line structure includes: providing an initial structure, the initial structure including active region structures; forming an initial bit line trench, the initial bit line trench exposing the active region structure; forming a conductive structure, the conductive structure being located at the bottom of the initial bit line trench; forming a bit line contact structure, the bit line contact structure covering the conductive structure, and a top surface of the bit line contact structure being lower than a top surface of the active region structure; and forming an insulation structure, the insulation structure covering the bit line contact structure.

Buried bit line structure, manufacturing method thereof, and semiconductor structure

A cleaning process for cleaning a surface of a semiconductor structure is provided, in which residue layer is formed on the surface of the semiconductor structure. The cleaning process includes providing a first reaction gas and a second reaction gas to the surface of the semiconductor structure, in which the first reaction gas reacts with the second reaction gas to remove the residue layer while forming a protection layer on the surface of the semiconductor structure.

Cleaning process and semiconductor processing method

A semiconductor manufacturing method includes: providing a semiconductor substrate, in which the semiconductor substrate includes an array region and a peripheral circuit region, in the array region, multiple capacitor contact holes are on the semiconductor substrate, and a first conductive layer is deposited on a bottom of each of the capacitor contact hole, and in the peripheral circuit region, a device layer is on the semiconductor substrate; treating the first conductive layer to increase its roughness; forming wire contact holes exposing the semiconductor substrate in the peripheral circuit region; forming a transition layer that at least covers a surface of the first conductive layer and a surface of the semiconductor substrate exposed by the wire contact holes; and forming a second conductive layer that covers the transition layer, and fills the capacitor contact holes and the wire contact holes.

Semiconductor device manufacturing method comprising first conductive layer with increased roughness in array region

A semiconductor structure includes a conductive structure. A method for preparing the conductive structure includes: forming a semiconductor conductive layer; forming a nitrile or isonitrile transition layer on the semiconductor conductive layer; and forming a metal conductive layer on the nitrile or isonitrile transition layer.

Semiconductor structure and method for preparing seminconductor structure

Provided are a semiconductor structure and a method for preparing the same. The method for preparing a semiconductor structure includes: a substrate is provided; a stacked structure is formed on the substrate; a first capacitor having a first bottom electrode, a first dielectric layer and a first top electrode is formed in the stacked structure, in which the first bottom electrode is of a columnar structure; and a second capacitor having a second bottom electrode, a second dielectric layer and a second top electrode is formed on the first capacitor, in which the second bottom electrode is of a concave structure. The second dielectric layer is formed between the second bottom electrode and the second top electrode, and the second dielectric layer is further formed between the second bottom electrodes of adjacent second capacitors.

Semiconductor structure with stacked capacitors

Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method for the semiconductor structure comprises: providing a substrate, wherein the substrate comprises active regions and isolation regions each located between the adjacent active regions, and each of the active regions comprises corner regions adjacent to the isolation regions; performing a doping process to implant doping ions into the corner regions, wherein the doping ions are configured to slow down an oxidation rate of the corner regions; and performing a removing process to remove the oxidized portion of the substrate after the doping process, wherein during the removing process, a side wall of each of the corner regions is exposed from a structure in the isolation region.

Semiconductor structure and manufacturing method thereof

A method for forming a silicon dioxide film and a method for forming a metal gate are provided. The method for forming a silicon dioxide film includes: forming a silicon dioxide layer on a semiconductor substrate, performing a nitrogen treatment to the silicon dioxide layer to convert the silicon dioxide layer of partial thickness into a mixed layer of silicon nitride and silicon oxynitride; and removing the mixed layer to form a silicon dioxide film on the semiconductor substrate.

Method for forming silicon dioxide film and method for forming metal gate

The present application discloses a semiconductor structure. The semiconductor structure includes: a substrate, the substrate being provided with a conductive structure; a first lower electrode and a second lower electrode sequentially stacked, the first lower electrode being located between the second lower electrode and the substrate, and the first lower electrode being electrically connected to the conductive structure; a first dielectric layer and a first upper electrode, the first dielectric layer covering a sidewall surface of the first lower electrode, and the first upper electrode being located on one side of the first dielectric layer away from the first lower electrode; and a second dielectric layer and a second upper electrode, the second dielectric layer covering an inner wall and a bottom surface of the second lower electrode, and the second upper electrode filling the recess of the second lower electrode.

Semiconductor structure and its manufacturing method

A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method of the semiconductor structure includes: providing a substrate; forming on an upper surface of the substrate first patterns each including a first main body and a first flank wall covering a sidewall of the first main body; forming a filling layer which covers the first flank wall and fills a gap between adjacent first patterns; and etching a top of each of the first patterns to obtain second main bodies, second flank walls and protrusions located on upper surfaces of the second flank walls, the second flank wall covering a sidewall of the second main body, and a top of the protrusion being at least higher than a top of the second main body.

A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes the following steps. A bit line structure is formed on a substrate. Each of the bit lines is provided with an insulation block on a side facing away from the substrate. A shielding portion is formed on a top of the insulation block that faces away from the substrate. A projection area of the shielding portion on the substrate is larger than a projection area of the insulation block on the substrate. An insulation sidewall is formed on a sidewall of the bit line and a sidewall of the insulation block, and a gap extending to the substrate is formed within the insulation sidewall corresponding to the shielding portion.

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Hefei, China

Bingyu Zhu