Yangtze Memory Technologies Co., Ltd.

Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.

Bin Yuan

Xiangning Wang

Zongke Xu

Qiangwei Zhang

Zhu Yang

Chen Zuo

Jingjing Geng

Zhen Guo

Cheng Chen

Fang Qin

Zhiliang Xia

Zongliang Huo

Bo Xu

ZongLiang Huo

Jiajia Wu

Zhaoyun Tang

Zhiguo Zhao

Rui Gong

Siying Liu

Song Man Xu

QingBo Liu

Cheng Zhou

Liming Cheng

Beibei Li

A semiconductor device includes a stack of alternating word line layers and insulating layers. The stack includes a core area, a stair step area, and, optionally, a dummy transition area connecting the core area to the stair step area. The semiconductor device also includes a gate line (GL) trench through the stack extending from the core area through the dummy transition area to the stair step area. The GL trench has a first width within the core area and a second width within the stair step area that is different from the first width. The semiconductor device also includes a first channel structure formed through the stack within the core area, and a stair step contact (SCT) formed through at least a portion of the stack within the stair step area. The SCT connects one of the word line layers of the stack within the stair step area.

Gateline mask design for removing sacrificial gateline polysilicon within stair step area

A three-dimensional (3D) memory device includes a staircase, a plurality of contacts, a plurality of groups of support structures, and a fourth support structure between adjacent groups of support structures through the staircase. The plurality of groups of support structures are arranged in a first direction. Each of the groups of support structures includes three support structures. Projections of the three support structures form a triangular shape in a plane parallel to the first direction. The plurality of contacts each is surrounded by a respective group. A projection of one of the contacts overlaps with the triangular shape of the respective group.

Three-dimensional memory devices and methods for forming the same

The present disclosure relates to a three-dimensional memory and a method for manufacturing the same. The three-dimensional memory includes a gate stack structure including a core area and a step area which are disposed in juxtaposition and in direct contact in a first direction; a dummy separation structure penetrating through the step area in the first direction; and a gate separation structure penetrating through the core area in the first direction, the gate separation structure having a first end in contact with the dummy separation structure in the first direction, the dummy separation structure having a second end in contact with the gate separation structure in the first direction, and the first end being located within the second end.

Three-dimensional memory and method for manufacturing the same

A gate drive circuit includes a plurality of gate drive units. Each of the gate drive units includes a stage transmission signal selection circuit, a pull-up control circuit, a pulse number reduction circuit, a first inversion circuit, a first output stage, and a second output stage, and can output a second gate control signal with a greater number of pulses and a first gate control signal with a less number of pulses. At least one of the stage transmission signal selection circuit, the first inversion circuit or the second output stage includes three transistors with the same channel type.

Gate drive circuits and display panels

Aspects of the disclosure provide methods for fabricating semiconductor devices. In some examples, a method for fabricating a semiconductor device includes forming a stack of layers having a first region and a second region. The stack of layers includes at least a first layer. The method then forms a hard mask layer on the stack of layers in the first region. Then, the method includes patterning the stack of layers in the second region of the semiconductor device. The patterning of the stack of layers in the second region removes a portion of the stack of layers in the second region, and exposes a side of the stack of layers. The method further includes covering at least the side of the stack of layers with a second layer that has a lower remove rate than the first layer, and then the method includes removing the hard mask layer.

Semiconductor device fabrication

The present disclosure provides a method for forming a three-dimensional (3D) memory. In an example, the method includes forming a stack structure having interleaved a plurality of stack first layers and a plurality of stack second layers, forming a stair in the stack structure, the stair having one of the stack first layers on a top surface, and forming a layer of sacrificial material having a first portion over a side surface of the stair and a second portion over the top surface of the stair. The method also includes partially removing the first portion of the layer of sacrificial material using an anisotropic etching process and removing a remaining portion of the first portion of the layer of sacrificial material using an isotropic etching process.

Methods for forming stairs in three-dimensional memory devices

Aspects of the disclosure provide semiconductor devices. For example, a semiconductor device includes a substrate having a first region and a second region along a first direction that is parallel to a main surface of the substrate. Then, the semiconductor device includes a memory stack that includes a first stack of alternating gate layers and insulating layers and a second stack of alternating gate layers and insulating layers along a second direction that is perpendicular to the main surface of the substrate. Further, the semiconductor device includes a joint insulating layer in the second region and a third stack of alternating gate layers and insulating layers in the first region between the first stack of alternating gate layers and insulating layers and the second stack of alternating gate layers and insulating layers.

Vertical memory devices

A three-dimensional (3D) memory device is provided. In an example, the 3D memory device includes a staircase and a plurality of groups of support structures through the staircase. The plurality of groups of support structures are arranged in a first direction, and each of the groups of support structures comprises three support structures, wherein projections of the three support structures form a triangular shape in a plane parallel to the first direction.

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, an isolation structure, and an alignment mark. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). The isolation structure extends vertically into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure. The alignment mark extends vertically into the substrate and is coplanar with the isolation structure.

Three-dimensional memory devices having isolation structure for source select gate line and methods for forming the same

A method for forming a 3D memory device is disclosed. The method includes: forming an first insulating layer on a substrate in a peripheral region, the first insulating layer having a slope near a boundary between the peripheral region and a core region of the substrate; forming an alternating conductive/dielectric stack on the substrate and the slope of the first insulating layer, a lateral portion of the alternating conductive/dielectric stack extending along a top surface of the substrate in the core region, and an inclined portion of the alternating conductive/dielectric stack extending along the slope of the first insulating layer; and forming a plurality of contacts to electrically contact a plurality of conductive layers in the inclined portion of the alternating conductive/dielectric stack.

Growing community of inventors

Hubei, China

Bin Yuan