Hong Kong Applied Science and Technology Research Institute Company, Limited

Bin Xie

Xunqing Shi

Chang Hwa Chung

Pui Chung Simon Law

Dan Yang

Jyh-Rong Lin

Yaofeng Sun

Wei Ma

Danting Xu

Yat Kit Tsui

Ou Dong

Chi Kuen Vincent Leung

Kin Lap Wong

Qingchun Li

Xuechao Liu

Yeung Yeung

A smart power hub has an AC port, a first DC port to a car battery, a second DC port to DC devices such as car instruments, and a third DC port to solar panels or another smart power hub. An AC bi-directional converter has six transistors in a B6 configuration to convert three-phase AC, acting as an interleaved totem-pole Power-Factor-Corrector for one-phase AC. A switch connects the DC bi-directional converter with either the AC bi-directional converter or the solar panels on the third DC port. A link capacitor has a DC link voltage that rises during battery charging. A DC bi-directional converter has a transformer, a primary bridge connected to the DC link voltage, and a secondary bridge of transistors connected to the first DC port. Auxiliary windings in the transformer drive a rectifier to the second DC port to power on-board DC devices. Solar DC charges the battery without AC conversion.

Smart power hub

The presently claimed invention provides a method for optimizing an electrodeposition process of a plurality of vias in a wafer. Instead of simulating a large number of via on the wafer for via filling, a representative via is selected with the maximum value of critical factor, which is a function of process parameters. The filling of the representative via is simulated with different sampling points to find out the filling goodness in order to find out the optimized process windows of process parameters. An optimizer is also disclosed, which either provides sampling points or reduces sampling points under artificial neural network method. Calculation of filling goodness is used for evaluating via filling quality and further comparing among via fillings simulated at different sampling points. Consequently, the method of present invention is able to shorten the simulation time for via filling as well as provide a process window with high accuracy.

Method for optimizing electrodeposition process of a plurality of vias in wafer

This invention discloses a through-silicon via (TSV) structure for providing an electrical path between a first-side surface and a second-side surface of a silicon chip, and a method for fabricating the structure. In one embodiment, the TSV structure comprises a via penetrated through the chip from the first-side surface to the second-side surface, providing a first end on the first-side surface and a second end on the second-side surface. A local isolation layer is deposited on the via's sidewall and on a portion of the first-side surface surrounding the first end. The TSV structure further comprises a plurality of substantially closely-packed microstructures arranged to form a substantially non-random pattern and fabricated on at least the portion of the first-side surface covered by the local isolation layer for promoting adhesion of the local isolation layer to the chip. A majority of the microstructures has a depth of at least 1 &#x3bc;m.

Through-silicon via structure with patterned surface, patterned sidewall and local isolation

The present invention provides a method for forming a three-dimensional wafer stack having a single metallized stack via with a variable cross-sectional shape. The method uses at least first and silicon wafers. Each wafer has one or more integrated circuits formed thereon. One or more through-vias are formed in each silicon wafer followed by oxide formation on at least an upper and lower surface of the silicon wafer. The wafers are aligned such that each wafer through via is aligned with a corresponding through via in adjacent stacked wafers. Wafers are bonded to form a three-dimensional wafer stack having one or more stack vias formed from the alignment of individual wafer vias. Via metallization is performed by depositing a seed layer in each of the stack vias followed by copper electroplating to form a continuous and homogeneous metallization path through the three-dimensional wafer stack.

Forming through-silicon-vias for multi-wafer integrated circuits

Subject matter disclosed herein may relate to packaging for multi-chip semiconductor devices as may be used, for example, in flash memory devices. In an example embodiment, a semiconductor chip may comprise a through-silicon via and a sidewall pad.

Semiconductor chip with through-silicon-via and sidewall pad

A method of aligning electronic components comprising providing a positioning memberhaving at least one formationfor receiving an electronic component; said at least one formation having lateral boundariesfor constraining movement of an electronic component; placing a first electronic componentin said at least one formation; and providing a force for actively aligning said first electronic component with a lateral boundary of said at least one formation. The force may, for example, be provided by tilting the positioning member, by providing suction or by using an actuator. An apparatus for aligning electronic components and a 3D system of stacked electronic components is also disclosed.

Apparatus for aligning electronic components

There is described a method of forming a through-silicon-via to form an interconnect between two stacked semiconductor components using pulsed laser energy. A hole is formed in each component, and each hole is filled with a plug formed of a first metal. One component is then stacked on another component such that the holes are in alignment, and a pulse of laser energy is applied to form a bond between the metal plugs.

Pulse-laser bonding method for through-silicon-via based stacking of electronic components

The subject matter disclosed herein relates to methods to reduce warpage of a substrate.

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Hong Kong, China

Bin Xie