Winbond Electronics Corporation

Bin-Shing Chen

Ching-Hsiang Hsu

Len-Yi Leu

Chi-Hung Chao

Evans Ching-Song Yang

Chiyeh Lo

Yimin Chen

A non-volatile memory cell that includes a semiconductor substrate, a well region implanted with a first-type dopant formed in the semiconductor substrate, a first doped region implanted with a second-type dopant formed in the semiconductor substrate, a second doped region, formed spaced-apart from the first doped region, implanted with a second-type dopant formed in the semiconductor substrate, the second doped region further including a third region implanted with the first-type dopant, a first dielectric layer disposed over the semiconductor substrate, a floating gate disposed over the first dielectric layer and extending over the well region and a portion of the second doped region, a second dielectric layer disposed over the floating gate, and a control gate disposed over the first dielectric layer and the second dielectric layer.

Split gate flash memory cell structure and method of manufacturing the same

A method is used to form a flash reference memory cell and comprises the following steps. A floating well is formed in a substrate. A first dielectric layer is formed to cover the substrate. A defined floating gate is formed on the first dielectric layer and aligned with the floating well. A second dielectric layer is formed on the substrate. A contact window is formed by defining the second dielectric layer to expose portions of the floating gate. A heavy ion implantation is performed on the exposed floating gate. A third dielectric layer is formed to cover the substrate and fills the contact window. The well region in the substrate is used as the isolation between the floating gate and the substrate to prevent the problems of over-etching in the contact window process and misalignment in the floating gate process. The heavy ion implantation process increases the amount of the dopant in the floating gate to reduce the resistance of the floating gate window, to improve the RC delay of the flash reference memory cell, and further to enhance the operation speed of the device.

Method for forming a flash reference cell

A process for producing a memory structure is disclosed. According to the process, an insulating portion and a conductive portion are formed with substantially equal thickness, and arranged in an alternate way to be a field oxide structure and a floating gate structure. This can be achieved by applying a conductive layer first, creating a trench in the conductive layer, filling the trench with an insulating material, and polishing the resulting layer. Because the insulating portion is formed adjacent to the conductive portion by filling the insulating material in the trench adjacent to the conductive portion, the field oxide structure and the floating gate structure are self-aligned while forming. Accordingly, no mis-alignment occurs, and thus the integration of the device can be improved. On the other hand, owing to the substantially equal thickness of the field oxide structure and the floating gate structure, the coupling effect between the floating gate structure and the control gate structure overlying the field oxide and the floating gate structures is well controlled, and thus the voltage for a programming or an erasing operation can be reduced.

Process for producing flash memory without mis-alignment of floating gate with field oxide

A method of Chisel programming in non-volatile memory by source bias. Whereby when reading and/or programming operations are executed, a body reading voltage and a body programming voltage are used. The method is comprised of changing the body programming voltage to reduce the difference between the changed body programming voltage and the body reading voltage and then running the programming operation utilizing the changed body programming voltage. Advantages include: elimination of the negative effects of parasitic capacitors in memory cells, simplification of bias circuit design, enhanced device reliability, and reduced disturbance.

Method of chisel programming in non-volatile memory by source bias

A process for making self-aligned split-gate non-volatile memory cell is disclosed. It includes the step of using a nitride photomask in conjunction with a photoresist to etch the nitride layer and cause it to become a stepped nitride layer having a high thickness region and a low thickness. Then a poly-1 photomask is used in conjunction with a photoresist to etch through a first portion of the low thickness region to expose an underlying poly-1 layer intended to be floating gate, wherein at the same time, a portion of the high thickness region adjacent to the first portion of the low thickness region is also etched to a reduced thickness. After poly-1 oxidation, a cell drain photomask is used in conjunction with a photoresist to etch through a second portion of the low thickness region using a nitride etch and an underlying poly-1 layer using a poly etch. The portion of the high thickness region adjacent to the second portion of the low thickness region is also etched to a reduced thickness during the nitride etch. With such a stepped nitride layer approach, the floating gate and cell drain are formed using the same nitride photomask, thus ensuring the self-alignment of the select gate relative to the floating gate and the cell drain.

Method of making select gate self-aligned to floating for split gate flash memory structure

A technique for forming an integrated circuit device having a self-aligned gate layer. The method includes a variety of steps such as providing a substrate, which is commonly a silicon wafer. Field isolation regions including a first isolation region and a second isolation region are defined in the semiconductor substrate. A recessed region is defined between the first and second trench isolation regions. The isolation regions are made using a reactive ion etching technique. A thickness of material such as polysilicon is deposited overlying or on the first isolation region, the second isolation region, and the active region. A step of selectively removing portions of the thickness of material overlying portions of the first isolation region and the second isolation region is performed, where the removing step forms a substantially planar material region in the recessed region. The substantially planar material region is self-aligned into the recessed region using the removing step.

Method of making polysilicon self-aligned to field isolation oxide

A technique for forming an integrated circuit device having a self-aligned gate layer and an overlying stacked gate. The method includes a variety of steps such as providing a substrate (,), which is commonly a silicon wafer. Field isolation regions (,) including a first isolation region and a second isolation region are defined in the semiconductor substrate. A recessed region is defined between the first and second isolation regions. The isolation regions (,) are made using a local oxidation of silicon process, which is commonly called LOCOS, but can be others. A thickness of material (,) such as polysilicon is deposited overlying or on the first isolation region, the second isolation region, and the active region. A step of selectively removing portions of the thickness of material overlying portions of the first isolation region and the second isolation region is performed, where the removing step forms a substantially planar material region in the recessed region. A stacked control gate layer is formed overlying the thickness of material.

Method of fabricating self-aligned stacked gate flash memory cell

A technique for forming an integrated circuit device having a self-aligned gate layer. The method includes a variety of steps such as providing a substrate (,), which is commonly a silicon wafer. Field isolation regions (,) including a first isolation region and a second isolation region are defined in the semiconductor substrate. A recessed region is defined between the first and second isolation regions. The isolation regions (,) are made using a local oxidation of silicon process, which is commonly called LOCOS, but can be others. A thickness of material (,) such as polysilicon is deposited overlying or on the first isolation region, the second isolation region, and the active region. A step of selectively removing portions of the thickness of material overlying portions of the first isolation region and the second isolation region is performed, where the removing step forms a substantially planar material region in the recessed region. The substantially planar material region is self-aligned into the recessed region using the removing step.

Method of fabricating self-aligned split gate flash memory cell

A process for making stacked gate memory cells which does not require the extra thermal cycle as in the conventional SAMOS process. It includes the steps of: (a) forming a silicon nitride layer on a wafer surface; (b) forming a diffusion pattern mask on the silicon nitride layer which includes a source line diffusion mask; (c) removing portions of the silicon nitride layer not covered by the diffusion pattern mask to expose a portion of the silicon substrate; (d) removing the diffusion pattern mask; (e) using the remaining portion of the silicon nitride as a mask to grow a field oxide layer in the silicon substrate; (f) forming a poly-1 layer, an interpoly dielectric layer, and a poly-2 layer on the wafer surface; (f) forming a SAMOS (self-aligned MOS) mask which contains a plurality of SAMOS strips perpendicular to the poly-1 strips, followed by SAMOS etching to form a plurality of stacked gates. The source diffusion mask is formed to have such a predetermined width that the field oxide layer is formed to contain bird beaks which merge with each other to form an interconnected field oxide bird's beak. Further, the interconnected field oxide bird's beak is formed to be thicker than the thickness of the interpoly dielectric layer so as to protect the portion of the silicon substrate not covered by the poly-1 strips from being trenched during the SAMOS etching process.

Method of making self-aligned flash memory cell to prevent source line

An improved process for fabricating flash memory cells with high control-gate-to-floating-gate coupling ratio is disclosed. The flash memory cell contains: (a) a substrate; (b) at least a pair of spaced-apart floating gates on the substrate, each of the floating gate has a pair of poly sidewall spacers; (c) a field oxide layer (FOX) partially recessed into the substrate; (d) an oxide/nitride/oxide (ONO) layer covering each of the floating gates; (e) a control gate covering the oxide/nitride/oxide layer and the field oxide layer. The design of the flash memory cell allows the field oxide layer to be wedged between the pair of floating gates and below the poly sidewall spacers. The poly sidewall spacers substantially increases the overlapping area between the control gate and the floating gate, thus allowing the control-gate-to-floating-gate coupling ratio and the performance of the flash memory to be enhanced. Also, since the field oxide layer and the floating gates are self-aligned, high density flash memory can be made from this process. Furthermore, the distance between the floating gates can be shorter than that limited by the underlying photolithography technology.

Method of making self-aligned stacked gate flush memory with high

A method for fabricating a split gate memory cell using the self-alignment technique to reduce the amount of misalignment is disclosed. The memory cell generally comprises a floating gate for storing a charge, a select gate for selecting one or more memory cell to operate thereon, a control gate, a buried source region and a buried drain region. Due to the structure of the memory cell, there is no read disturbance when reading the memory cell and its low voltage requirement makes it suitable for low voltage applications. When placed in a memory array, each of the memory cells in the array can be individually programmed or read. In performing the erase operation, a column of information is erased.

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Hsinchu, Taiwan

Bin-Shing Chen