International Business Machines Corporation

Bijan Davari

Ghavam G Shahidi

Devendra K Sadana

Dinesh C Verma

Shahrokh Daijavad

Jack Allan Mandelman

Sandip Tiwari

Effendi Leobandung

Carl John Radens

Tze-Chiang Chen

Gary Bela Bronner

Johann Greschner

Howard L Kalter

Werner A Rausch

H Bernhard Pogge

Dan Moy

Scott R Stiffler

George A Sai-Halasz

Brian Naughton

Louis L Hsu

Keith E Fogel

Wei Hwang

David Louis Harame

Raghu Kiran Ganti

Fariborz Assaderaghi

Vadim Sheinin

Barbara A Chappell

Nirmit V Desai

Nicky C Lu

Heather D Achilles

Gheorghe Almasi

Yuan Taur

Octavian Popescu

Wendy Chong

Kwang Su Choe

Robert E Bendernagel

Joe Latone

Eti Ganin

Kelvin Kakugwa

An embodiment of the present invention is a prime representation data structure in a computer architecture. The prime representation data structure has a plurality of records where each record contains a prime representation and where the prime representation is a product of two or more selected prime factors. Each of the selected prime factor associated with an n-gram of a domain representation of a domain string. The domain representation of the domain string is a domain string of ordered, contiguous domain characters. The n-gram being a subset of n number of the ordered, contiguous domain characters in the domain string. The computer architecture performs string searching and includes one or more central processing units (CPUs) with one or more operating systems, one or more input/output device interfaces, one or more memories, and one or more input/output devices. The architecture further includes the prime representation data structure, one or more prime target query data structures and a search process performed by one or more of the CPUs. The CPUs can be organized in a hierarchical structure. The prime target query data structure has one or more target prime queries. Each target prime query is the product of one or more target selected prime factors. Each target selected factor is associated with a target n-gram of a target domain representation of a target domain string. The search process, performed by one or more of the CPUs, determines whether one or more of the target selected prime factors is common with one of the selected prime factors. By performing this efficient testing, the computer system can determine if one or more small strings are included in one or more large strings.

Computer architecture for string searching

Personalization with on-device privacy preservation is provided by receiving, at a user device, a generalized recommendation from a remote provider backend, which include a plurality of candidate items responsive to a request from an application running on the user device; generating a plurality of candidate vectors corresponding to the plurality of candidate items representing a corresponding candidate item in a binary format across a plurality of metrics associated with the plurality of candidate items; generating a user vector based on personal data stored on the user device, the user vector representing a user in a binary format across one or more metrics associated with the personal data; determining interaction propensities based on the user vector and the plurality of candidate vectors according to a global model run on the user device; and displaying, on the user device, the plurality of candidate items according to the interaction propensities.

On-device privacy-preservation and personalization

A cloud-enterprise resource management system enables sharing of computing resources belonging to different datacenters by one or more clients of a resource pooling and sharing service. Each datacenter of includes a first partition of computing resources and a second partition of computing resources. The first partition is designated as reserved for use by an enterprise operating the datacenter. The second partition is designated as available for use by one or more clients of the resource pooling and sharing service. A workload manager in each datacenter predicts workload and transfers (i) a first computing resource from the first partition to the second partition wherein when the predicted workload is below a first threshold and (ii) a second computing resource from the second partition to the first partition when the predicted workload is above a second threshold.

Shared enterprise cloud

A set of network traffic among a plurality of legacy applications is monitored. From the set of network traffic, a communication graph is generated for the plurality. From the communication graph, a set of migratable applications within the plurality is identified. The set of migratable applications is migrated to a cloud edge layer, and a user is notified of the migration.

Migrating complex legacy applications

Techniques for reconfiguring mobile networks based on network state information are provided. In one aspect, a method for managing a mobile network is provided. The method includes the steps of: gathering network state information from an edge of the mobile network, wherein the edge of the mobile network includes a radio network and a cellular network through which user equipment communicate with an internet protocol (IP) network which is at a core of the mobile network; analyzing the network state information based on policy controls to determine actions for optimizing the mobile network; and reconfiguring the mobile network using the actions for optimizing the mobile network. A system for managing a mobile network is also provided.

Reconfiguring a mobile network based on cellular network state information

Techniques for improving real-time communications over a mobile network are provided. In one aspect, a method for managing data transfer in a mobile network wherein user equipment transmit data through one or more cell towers is provided. The method includes the steps of: intercepting data packets from the user equipment; determining a location of a given one of the cell towers in the mobile network to which the data packets are to be sent; and tunneling the data packets directly to the given cell tower. A system for managing data transfer in a mobile network wherein user equipment transmit data through one or more cell towers is also provided.

IP based real-time communications over a mobile network

A patterned SOI/SON composite structure and methods of forming the same are provided. In the SOI/SON composite structure, the patterned SOI/SON structures are sandwiched between a Si over-layer and a semiconductor substrate. The method of forming the patterned SOI/SON composite structure includes shared processing steps wherein the SOI and SON structure are formed together. The present invention also provides a method of forming a composite structure which includes buried conductive/SON structures as well as a method of forming a composite structure including only buried void planes.

Formation of patterned silicon-on-insulator (SOI)/silicon-on-nothing (SON) composite structure by porous Si engineering

A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep, trench in bulk Si while forming merged logic regions on SOI.

Patterned SOI regions on semiconductor chips

A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silicon substrate. The trench capacitor is formed in the substrate and the access transistor is formed on a sidewall of the SOI layer. A polysilicon strap connected to the polysilicon plate of the storage capacitor provides a self-aligned contact to the source of the access transistor. Initially, the buried oxide layer is formed in the wafer. Deep trenches are etched, initially just through the SOI layer and the BOX layer. Protective sidewalls are formed in the trenches. Then, the deep trenches are etched into the substrate. The volume in the substrate is expanded to form a bottle shaped trench. A polysilicon capacitor plate is formed in the deep trenches and conductive polysilicon straps are formed in the trenches between the capacitor plates and the SOI sidewalls. Device regions are defined in the wafer and a sidewall gate is formed in the deep trenches. Shallow trenches isolation (STI) is used to isolate and define cells. Bitlines and wordlines are formed on the wafer.

Silicon-on-insulator vertical array device trench capacitor DRAM

A silicon on insulator (SOI) dynamic random access memory (DRAM) cell, array and method of manufacture. The memory cell includes a vertical access transistor above a trench storage capacitor in a layered wafer. A buried oxide (BOX) layer formed in a silicon wafer isolates an SOI layer from a silicon substrate. Deep trenches are etched through the upper surface SOI layer, the BOX layer and into the substrate. Each trench capacitor is formed in the substrate and, the access transistor is formed on a sidewall of the SOI layer. Recesses are formed in the BOX layer at the SOI layer. A polysilicon strap recessed in the BOX layer connects each polysilicon storage capacitor plate to a self-aligned contact at the source of the access transistor. Dopant is implanted into the wafer to define device regions. Access transistor gates are formed along the SOI layer sidewalls. Shallow trenches are formed and filled with insulating material to isolate cells from adjacent cells. Wordlines and bitlines are formed to complete the memory array.

Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap

A process for making a capacitor for a silicon-on-insulator (SOI) structure. The SOI structure has a p-type silicon base layer, a buried oxide layer, a silicon layer, and an n layer formed within a portion of the p-type silicon base layer. The process comprises the steps of forming a buried oxide layer and a silicon layer in the p-type silicon base layer, forming an n layer in a portion of the p-type silicon base layer, and forming electrically conductive paths to the p-type silicon base layer and the n layer extending through the buried oxide and silicon layers.

Process of making buried capacitor for silicon-on-insulator structure

A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep trench in bulk Si while forming merged logic regions on SOI.

Patterned SOI regions in semiconductor chips

A process for making a capacitor for a silicon-on-insulator (SOI) structure. The SOI structure has a p-type silicon base layer, a buried oxide layer, a silicon layer, and an n,layer formed within a portion of the p-type silicon base layer. The process comprises the steps of forming a buried oxide layer and a silicon layer in the p-type silicon base layer, forming an n,layer in a portion of the p-type silicon base layer, and forming electrically conductive paths to the p-type silicon base layer and the n,layer extending through the buried oxide and silicon layers.

Buried capacitor for silicon-on-insulator structure

A method for fabricating an integrated circuit package or arrangement includes providing a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having conversely matching bottom surface topographies to permit self-aligned positioning of the chip on the carrier. Chips are provided such that top faces of neighboring chips lie substantially in planes separated by a distance of greater than 0.0 .mu.m. The carrier is arranged and dimensioned such that the neighboring chips are separated by a gap G or spacing in a range of 1 .mu.m&lt;G.ltoreq.100 .mu.m. A metallic interconnect is provided over the top faces and the gap. Preferably, the interconnect has a gradual slope over the gap.

Method for fabricating a very dense chip package

An integrated circuit package or arrangement includes a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having conversely matching bottom surface topographies to permit self-aligned positioning of the chips on the carrier. Top faces of neighboring chips lie substantially in planes separated by a distance of greater than 0.0 .mu.m. The neighboring chips are separated by a gap G or spacing in a range of approximately 1 .mu.m&lt;G.ltoreq.approximately 100 .mu.m. A metallic interconnect is disposed over the top faces and the gap. Preferably, the interconnect has a gradual slope over the gap.

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Mahopac, NY, United States of America

Bijan Davari