Lam Research Corporation

Bi Ming Yen

Sean S Kang

David Wei

Vinay Pohray

Binet A Worsham

Rajinder Dhindsa

Andrew D Bailey, Iii

Eric A Hudson

Alexei Marakhtanov

Hong Shih

James Rogers

Peter K Loewenhardt

Chun Yan

Keren Jacobs Kanarik

Gerardo Delgadino

Tuochuan Huang

Jerome S Hubacek

Catherine Zhou

Enrico Magni

C Robert Koemtzopoulos

Daxing Ren

Xingcai Su

Dae J Lim

Dougyong Sung

Methods, systems, and computer programs are presented for semiconductor manufacturing are provided. One wafer processing apparatus includes: a top electrode; a bottom electrode; a first radio frequency (RF) power source; a second RF power source; a third RF power source; a fourth RF power source; and a switch. The first, second, and third power sources are coupled to the bottom electrode. Further, the switch is operable to be in one of a first position or a second position, where the first position causes the top electrode to be connected to ground, and the second position causes the top electrode to be connected to the fourth RF power source.

Triode reactor design with multiple radiofrequency powers

A blank wafer is placed in an etch chamber. A layer is deposited over the blank wafer, comprising providing a deposition gas, forming the deposition gas into a deposition plasma, and stopping the deposition gas. The blank wafer with the deposited layer is removed from the etch chamber. The thickness of the deposited layer is measured. Wafer temperature accuracy is calculated from the measured thickness of the deposited layer. The etch chamber is compensated according to the calculated wafer temperature accuracy. A wafer with an etch layer over the wafer and a patterned mask over the etch layer is placed into the etch chamber. The etch layer is etched in the etch chamber.

Process for wafer temperature verification in etch tools

A method for etching features in a silicon oxide based dielectric layer over a substrate, comprising performing an etch cycle. A lag etch partially etching features in the silicon oxide based dielectric layer is performed, comprising providing a lag etchant gas, forming a plasma from the lag etchant gas, and etching the etch layer with the lag etchant gas, so that smaller features are etched slower than wider features. A reverse lag etch further etching the features in the silicon oxide based dielectric layer is performed comprising providing a reverse lag etchant gas, which is different from the lag etchant gas and is more polymerizing than the lag etchant gas, forming a plasma from the reverse lag etchant gas, and etching the silicon oxide based dielectric layer with the plasma formed from the reverse lag etchant gas, so that smaller features are etched faster than wider features.

Lag control

Methods for cleaning an electrode assembly, which can be used for etching a dielectric material in a plasma etching chamber after the cleaning, comprise polishing a silicon surface of the electrode assembly, preferably to remove black silicon contamination therefrom.

Methods for silicon electrode assembly etch rate and etch uniformity recovery

A semiconductor chip formed on a substrate is provided. An oxygen-doped silicon carbide etch stop layer is formed over the substrate. An organosilicate glass layer is formed over the oxygen-doped silicon carbide etch stop layer. A feature is selectively etched in the organosilicate glass layer using an etch with an organosilicate glass to oxygen-doped silicon carbide selectivity greater than 5:1.

Method for selectively etching organosilicate glass with respect to a doped silicon carbide

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Fremont, CA, United States of America

Bi Ming Yen