Taiwan Semiconductor Manufacturing Comp. Ltd.

Bi-Ling Lin

Jiaw-Ren Shih

Jian-Hong Lin

Chung-Hui Chen

Wei-Chih Chen

Chii-Ping Chen

Wen-Sheh Huang

Wan-Te Chen

Sheng-Feng Liu

Chun-Wei Chang

Chung-Cheng Wu

Ming-Hong Hsieh

Yung-Sheng Tsai

Chwei-Ching Chiu

Shou-En Liu

Carlos Hernando Diaz

Chien Shih Tsai

Lee-Der Chen

Chin Chuan Peng

Chien-Jung Wang

Yi-Lung Cheng

Tzu-Li Lee

Jyh-Haur Wang

Huey-Liang Hwang

Shou-Chung Lee

Bor-Jou Wei

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a resistive element over the substrate. The semiconductor device structure also includes a thermal conductive element over the substrate. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line, and the first imaginary line and the second imaginary line intersect at a center of the main surface.

Semiconductor device structure with resistive element

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. The thermal conductive element at least partially overlaps the resistive element. In addition, the semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.

A method includes identifying fingers of a first device and fingers of a second device. The method includes grouping the fingers of the first device into a first finger group and a second finger group, wherein the first finger group is electrically connected to the second finger group. The method further includes positioning the first finger group extends across a first doped region. The method further includes positioning the second finger group extends across a second doped region, wherein the second doped region has a same dopant type as the first doped region. The method further includes grouping the fingers of the second device into a third finger group and a fourth finger group, wherein the third finger group is electrically connected to the fourth finger group. The method further includes positioning the third finger group and the fourth finger group extending across the second doped region.

Circuit layout method

A circuit layout includes a first device having a first set of fingers, wherein the first set of fingers is separated into a first finger group and a second finger group, the first finger group comprising a first number of fingers, and the second finger group comprising a second number of fingers. The circuit layout further includes a second device having a second set of fingers, wherein the second set of fingers includes a third finger group having a third number of fingers. The first finger group, the second finger group and the third finger group extend across a first doped region, and the third finger group is between the first finger group and the second finger group.

Circuit layout, layout method and system for implementing the method

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line. The first imaginary line and the second imaginary line intersect at a center of the main surface. The semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.

Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.

Semiconductor device components and methods

A semiconductor structure for dissipating heat away from a resistor having neighboring devices and interconnects. The semiconductor structure includes a semiconductor substrate, a resistor disposed above the semiconductor substrate, and a thermal protection structure disposed above the resistor. The thermal protection structure has a plurality of heat dissipating elements, the heat dissipating elements having one end disposed in thermal conductive contact with the thermal protection structure and the other end in thermal conductive contact with the semiconductor substrate. The thermal protection structure receives the heat generated from the resistor and the heat dissipating elements dissipates the heat to the semiconductor substrate.

Method and structure for dissipating heat away from a resistor having neighboring devices and interconnects

A method for measuring a property of interconnections is provided. The method includes the following steps. A plurality of interconnection test patterns are provided. A pad to which the plurality of interconnection test patterns are parallelly connected is formed. At least one resistor is formed between at least one of the plurality of interconnection test patterns and the pad. The property of the plurality of interconnection test patterns is measured by applying a current, a voltage and/or a mechanical stress to the pad.

Method for measuring a property of interconnections and structure for the same

A method for forming FET devices with attenuated gate induced drain leakage current. There is provided a silicon semiconductor substrate employed within a microelectronics fabrication. There is formed within the silicon substrate field oxide (FOX) dielectric isolation regions defining an active silicon substrate device area. There is formed over the substrate a silicon oxide gate oxide insulation layer employing thermal oxidation. There is then formed over the silicon oxide gate oxide insulation layer a patterned polycrystalline silicon gate electrode layer. There is then thermally oxidized the substrate and polycrystalline silicon gate electrode to form a thicker silicon oxide layer at the edge of the gate electrode and in the adjacent silicon substrate area. There is then etched back the thicker silicon oxide layer from the silicon substrate area adjacent to the gate electrode. There is then formed employing low energy ion implantation shallow junction source-drain extension regions adjacent to the gate electrode. There is then formed source-drain regions to complete the FET device, which exhibits attenuated drain leakage current. The present invention may be employed to fabricate complementary metal-oxide-silicon (CMOS) FET devices of either polarity with attenuated gate induced drain leakage (GIDL) current, short channel effect (SCE) and punch-through leakage current in integrated circuit microelectronics fabrications wherein low power drain is desired.

Method to reduce the gate induced drain leakage current in CMOS devices

A method for forming within a substrate employed within a microelectronics fabrication a field effect transistor with attenuated drain leakage current. There is provided a silicon substrate within which are fabricated nMOS field effect transistors (FET) with lightly-doped n-type drain regions (nLDD) employing arsenic (As) dopant. There is then implanted indium (In) dopant atoms adjacent to the As diffused junction to form a p-type pocket therein. There is then avoided the customary high temperature rapid thermal annealing (RTA) step and instead employed a thermal annealing for 2 hours at 750 degrees centigrade, whereupon the implanted indium atom undergo transient enhanced diffusion (TED) to form a graded junction profile, resulting in attenuated drain leakage current and no increased reverse short channel effect from the strong segregation of indium into silicon oxide.

Drain leakage reduction by indium transient enchanced diffusion (TED) for low power applications

Methods are disclosed for depositing an in situ polysilicon layer on the back of a semiconductor wafer to reduce the temperature at the edge of the wafer during rapid thermal annealing (RTA). The reduced temperature results in decreased boron penetration at the edge of the wafer and a more uniform silicide resistance and threshold voltage across the wafer.

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Hsinchu, Taiwan

Bi-Ling Lin