International Business Machines Corporation

Bhupender Singh

Charles Leon Arvin

Mark William Kapfhammer

Thomas Weiss

Shidong Li

Richard Francis Indyk

Brian W Quinlan

Jon Alfred Casey

Thomas Anthony Wassick

Steve Ostrander

Sylvain Pharand

Chris Muzzy

Krishna R Tunga

Steven Paul Ostrander

Thomas Edward Lombardi

Glenn A Pomerantz

Tuhin Sinha

Sylvain E Ouimet

Joseph C Sorbello

Rachel E Olson

Joseph Jacobi

A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.

High bandwidth module

An integrated circuit package structure is provided that includes a chip carrier substrate, at least one processor die provided on the chip carrier substrate, a plurality of lateral escape wiring lines connected to and extending away from the at least one processor die, and a plurality of chips at least partially surrounding the processor die, at least one of the chips overlapping with at least one of the lateral escape wiring lines in a plan view. An interconnect structure of the chips includes at least one vertical power feed structure that is configured and positioned not to intersect with the lateral escape wiring lines in the plan view.

Near tier decoupling capacitors

A multi-die integrated circuit device and a method of fabricating the multi-die integrated circuit device involve a substrate. Two or more dice include components that implement functionality of the multi-die integrated circuit. The components include logic gates. The multi-die integrated circuit device also includes a spacer disposed between the substrate and each of the two or more dice. Each of the two or more dice makes direct electrical contact with the substrate without making direct electrical contact with the spacer through holes in the spacer.

Spacer for die-to-die communication in an integrated circuit and method for fabricating the same

An electronic system includes two integrated circuit (IC) packages that are connected by a package to package (PP) connector. The PP connector may include cabling between a first cabling connector and a second cabling connector. The first cabling connector may be seated to a first carrier connector upon a first IC device carrier of the first IC device package. The second cabling connector may be seated to a second carrier connector upon a second IC device carrier of the second IC device package. The electronic system may further include a heat sink connected to the IC packages, to the first cabling connector, and to the second cabling connector. An IC device may route I/O data through the PP connector, effectively increasing the number of I/O routes.

Polygon integrated circuit (IC) packaging

An integrated circuit package includes a substrate, a flip chip die, and a capacitor. The flip chip die is attached to the substrate via die-to-substrate interconnects. The capacitor is attached to the flip chip die via capacitor-to-die interconnects so that the capacitor occupies a region between the flip chip die and the substrate. Such placement of the capacitor on a flip chip die has the advantage of reducing the distance between the capacitor and its core, thereby reducing unwanted line inductance and series resistance effects. Integrated circuit performance is thereby enhanced.

Direct attachment of capacitors to flip chip dies

An alignment carrier, assembly and methods that enable the precise alignment and assembly of two or more semiconductor die using an interconnect bridge. The alignment carrier includes a substrate composed of a material that has a coefficient of thermal expansion that substantially matches that of an interconnect bridge. The alignment carrier further includes a plurality of solder balls located on the substrate and configured for alignment of two or more semiconductor die.

Alignment carrier for interconnect bridge assembly

An electrical device includes an electrically insulating body having an insulating body surface and a conductive pad array, a small conductive pad arranged on the insulating body surface and within the conductive pad array, and an enlarged conductive pad. The enlarged conductive pad is arranged on the insulating body and within the conductive pad array, wherein the enlarged conductive pad is spaced apart from the small conductive pad and is larger than the small conductive pad. C4 assemblies and methods of making C4 assemblies including the electrical device are also described.

Enlarged conductive pad structures for enhanced chip bond assembly yield

An electronic apparatus that includes a first semiconductor chip mounted on a substrate; a second semiconductor chip mounted on the substrate; a spacer attached to the substrate and situated between the first and second semiconductor chips; a lid mounted on the substrate and enclosing the first and second semiconductor chips and the spacer, the spacer having an adhesive material adhesively attached to the lid; and underfill material underneath the first and second semiconductor chips, underneath the spacer and between the spacer and the first and second semiconductor chips.

Electronic apparatus having inter-chip stiffener

Semiconductor structures are provided in which a first chip on a substrate has at least one first protruding section, the first protruding section including first interconnect locations, a second chip on the substrate having at least one second protruding section, the second protruding section including second interconnect locations and the first chip and the second chip are arranged such that the first protruding section is interdigitated with the second protruding section.

Fins for enhanced die communication

Spacer for die-to-die communication in an integrated circuit

A device including a substrate, an upper capacitor, and a lower capacitor is described. The upper capacitor is mounted on the substrate and includes an upper body and a pillar that extends from the upper body towards the substrate. The lower capacitor includes a lower body that is disposed both lateral to the pillar and at least in part between the upper body and the substrate. Each of the upper capacitor and the lower capacitor is a respective discrete circuit component. Such capacitor stacking configurations facilitate the placement of larger numbers of capacitors in close proximity to microprocessor cores in integrated circuit modules without the need to increase module size.

Growing community of inventors

Fishkill, NY, United States of America

Bhupender Singh