Advanced Micro Devices Corporation

Spansion Llc.

Bhimachar Venkatesh

Sameer Wadhwa

Michael Achter

Takao Akaogi

Michael Allen Van Buskirk

Ming-Huei Shieh

Edward V Bautista, Jr

Vikram S Santurkar

A sense amplifier includes a reference voltage generator for generating a reference output voltage and a core output voltage generator for generating a core output voltage. The core output voltage generator includes a core front-end stage and a core back-end stage or includes a plurality of amplifier transistors each conducting a portion of a core current through a current conducting device such as core cell. The sizes and/or connections of transistors of such components result in high voltage swing and thus high sensitivity of the sense amplifier.

Sense amplifiers with high voltage swing

The present invention pertains to a circuit arrangement that, in one example, facilitates reading or determining an amount of current that flows through a memory cell when one or more voltages are applied to the cell. The amount of current resulting from the applied voltages is a function of the amount of charge stored within the cell, among other things, and the amount of stored charge represents information stored within the cell. As such, reading the resulting current allows data stored within the cell to be accessed and retrieved. It will be appreciated however, that use of the circuitry disclosed herein is not limited to memory applications. Rather, it can be used in any application where current sensing is required along with a regulated supply voltage.

Current sensing architecture for high bitline voltage, rail to rail output swing and Vcc noise cancellation

A circuit is disclosed that compensates for changes in temperature as well as for fluctuations in a supply voltage (Vcc) so that voltage reference values generated thereby are maintained at substantially constant levels irrespective of changes in temperature or fluctuations in supply voltage. The circuit is also configured to produce a wide range of voltage reference values so that it can independently service the needs of many different applications. Additionally, the circuit is designed using meal oxide semiconductor (MOS) technology, as opposed to more conventional bipolar technology, so that it 'settles down' or generates reference values relatively quickly.

Fast wide output range CMOS voltage reference

The present invention facilitates more accurate data reads by compensating for parasitic behavior&#x2014;thus regulating the voltage at the drain of a core memory cell rather than at the output of a sensing circuit. More particularly, respective voltages at one or more nodes, such as the start of a bitline at a sensing circuit, for example, are adjusted to compensate for voltage drops that may occur due to parasitic behavior. Maintaining the substantially constant voltage levels at core memory cells allows comparisons to be made under ideal conditions while reducing the side leakages in virtual ground schemes. This mitigates margin loss and facilitates more reliable data sensing.

Current sensing circuit with a current-compensated drain voltage regulation

The present invention discloses a method of providing a voltage to a plurality of wordlines during the Automatic Program Disturb Erase Verify (APDEV) operation in a memory device. During the APDEV operation, the voltage is supplied to the wordlines sequentially from two energy sources; a charge share circuit and a temperature compensated bias generator circuit. The respective voltages from the two energy sources are applied to the wordlines to charge the wordlines to a bias voltage. The bias voltage is the appropriate voltage on the wordlines to allow the memory device to verify that the bitline current flow is not excessive in the erased memory sector at the present operating temperature of the memory device. The amount of voltage needed to create the bias voltage is dependent on the operating temperature of the memory device.

Charge sharing to help boost the wordlines during APDE verify

The present invention discloses methods and systems for generating a bias voltage during an Automatic Program Disturb Erase Verify (APDEV) operation in a memory device. During the APDEV operation, a predetermined supply voltage is generated by a regulated power supply. The predetermined supply voltage is directed to a temperature-compensated bias generator circuit. The temperature-compensated bias generator circuit is activated to generate the bias voltage based on the operating temperature of the memory device.

Temperature-compensated bias generator

An integrated circuit (,) includes an array of memory cells (,), each memory cell coupled to a word line (,) and a bit line (,). The integrated circuit further includes a first external connection (,) configured to receive a variable voltage and a second external connection (,) configured to provide an operating parameter of the integrated circuit. First logic circuitry (,) is coupled to the first external connection and word lines of the array of memory cells and is configurable in one of a normal mode and a test mode in response to a first control signal. The first logic circuitry conveys the variable voltage to the array in the test mode.

Method and apparatus for measuring subthreshold current in a memory array

A page mode memory senses a large number of bits simultaneously. The associated read current creates a source bias in the core cells which alters the sense margin at the sense amplifier. To address this problem, a memory integrated circuit (100) includes an array (102) of core cells, each core cell having a ground node (220, 222, 224). A ground line (230) couples the ground node of each core cell to a ground potential (Vss) and establishes a variable parasitic potential between the ground node and Vss. For sensing the data state of the core cells, a reference core cell (252) matches the array core cells and has a reference ground node (262). A circuit element (256) is coupled between the reference ground node and Vss to establish a variable reference potential to match the variable parasitic potential.

Source bias compensation for page mode read operation in a flash memory

A CMOS address transition detector includes a first input circuit section, a first delay circuit section, a second input circuit section, a second delay circuit section and an output circuit section. The first input circuit section and the first delay circuit section are responsive to true address transition signals for controlling the pulse width of an output pulse signal. The second input circuit section and the second delay circuit section are responsive to a false address transition signal for controlling the pulse width of the output signal. The output circuit section generates at an output terminal the output pulse signal having a pulse width which is substantially constant over a wide temperature range. The output circuit section has a first input which is responsive to the first input circuit section and the first delay circuit section when the true address transition signal makes a low-to-high transition. The output circuit section has a second input which is responsive to the second input circuit section and the second delay circuit section when the false address transition signal makes a low-to-high transition.

CMOS address transition detector with temperature compensation

A high voltage isolation circuit for CMOS networks includes a N-channel MOS pass transistor for isolating a high voltage node from a low voltage node so as to prevent CMOS latch-up. There is provided a substrate of N-conductivity type and a P-conductivity region diffused in the substrate to form a PN junction. A supply potential is applied to the substrate. The pass transistor has a conduction path and a control electrode in which one end of the conduction path defines a first node for receiving thereat a first voltage, and the other end of the conduction path defines a second node for receiving thereat a second voltage. The first node is connected to the P-conductivity region. During a first mode of operation, the pass transistor is rendered more conductive so that the first node is coupled to the second node so that the second voltage follows the first voltage. During a second mode of operation, the pass transistor is rendered less conductive so that the second node is isolated from the first node so that the second voltage, which is allowed to be charged higher than the supply potential, is prevented from being applied to the P-conductivity region thereby avoiding latch-up.

High voltage isolation circuit for CMOS networks

A CMOS current sense amplifier circuit for providing a high speed of operation includes a sense amplifier, a dummy sense amplifier and an operational sense amplifier. A memory array is formed of a plurality of core transistors which are arranged in a plurality of rows of word lines and a plurality of columns of bit-lines. A dummy bit-line is formed of a plurality of core transistors which are arranged in parallel along the rows of word lines. A first pass transistor and a plurality of Y-pass transistors are coupled between the sense amplifier and the memory array. Second and third pass transistors are coupled between the dummy sense amplifier and the dummy bit-line. A plurality of N-channel MOS transistors are used to clamp all of the bit-lines in the array and dummy bit-line to a ground potential. The operational sense amplifier is responsive to the sense amplifier, dummy sense amplifier and the clamping transistors for generating an output signal which has a fast response time when making a low-to-high transition (that is when selecting an unprogrammed memory cell).

High speed CMOS current sense amplifier

A temperature compensated active resistor for use on an integrated circuit semiconductor chip is formed of a N-channel MOS transistor, a string of first, second and third transistors connected as a series of diodes, and a P-channel MOS transistor. The P-channel MOS transistor has its drain electrode connected to an output terminal in which a resistance value at the output terminal remains substantially constant over a relatively wide temperature range.

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Cupertino, CA, United States of America

Bhimachar Venkatesh