Lam Research Corporation

International Business Machines Corporation

Bhaskar Nagabhirava

Michael Goss

Prabhakara Gopaladasu

Peng Wang

Adarsh Basavalingappa

Stefan Schmitz

Randolph F Knarr

Dominik Metzler

Ananth Indrakanti

Phil Friddle

Phillip Friddle

Yann Mignot

Nelson M Felix

Tom K Choi

Alan John Jensen

Jennifer Church

Seongjun Heo

Ekimini Anuja De Silva

Chih-Hsiang Wu

Ying-Ren Chen

Various embodiments herein relate to methods, apparatus, and systems that utilize a multi-layer hardmask in the context of patterning a semiconductor substrate using extreme ultraviolet photoresist. The multi-layer hardmask includes (1) an upper layer that includes a metal-containing material such as a metal oxide, a metal nitride, or a metal oxynitride, and (2) a lower layer that includes an inorganic dielectric silicon-containing material. Together, these layers of the multi-layer hardmask provide excellent etch selectivity and reduce formation of defects such as microbridges and line breaks. Certain embodiments relate to deposition of the multi-layer hardmask. Other embodiments relate to etching of the multi-layer hardmask. Some embodiments involve both deposition and etching of the multi-layer hardmask.

Multi-layer hardmask for defect reduction in EUV patterning

Methods of patterning vias and trenches using a polymerization protective liner after forming a lower patterned mask layer used for etching trenches on a semiconductor substrate prior to forming an upper patterned mask layer used for etching vias are provided. Methods involve forming a polymerization protective liner either nonconformally or conformally using silicon tetrachloride and methane polymerization. Polymerization protective liners may be sacrificial.

Polymerization protective liner for reactive ion etch in patterning

A method for selectively etching an etch layer with respect to a mask is provided. An etch process is provided comprising a plurality of etch cycles, wherein each etch cycle comprises providing a deposition phase and an etch phase. The deposition phase comprises providing a flow of a deposition phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio, providing a RF power, which forms the deposition phase gas into a plasma, and stopping the deposition phase. The etch phase, comprises providing a flow of an etch phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio that is lower than the fluorocarbon or hydrofluorocarbon to oxygen ratio of the deposition phase gas, providing a RF power, and stopping the etch phase.

Method for selectively etching with reduced aspect ratio dependence

A method for selectively etching trenches in a silicon oxide containing layer with an organic planarization layer is provided. Processing the silicon oxide layer comprises a plurality of process cycles, wherein each etch cycle comprises a deposition phase, comprising providing a flow of a deposition phase gas comprising a fluorocarbon or hydrofluorocarbon containing gas with a fluorine to carbon ratio, providing a constant RF power, which forms the deposition phase gas into a plasma, and stopping the deposition phase and an etch phase, comprising providing a flow of an etch phase gas comprising a fluorocarbon or hydrofluorocarbon containing gas with a fluorine to carbon ratio that is higher than the fluorine to carbon ratio of the deposition phase gas, providing a pulsed RF power, which forms the etch phase gas into a plasma, and stopping the etch phase.

Method for selectively etching silicon oxide with respect to an organic mask

A method for selectively etching silicon nitride with respect to silicon oxide is provided. An oxygen free silicon nitride etch gas comprising Hand either CFor CHF(X&#x2267;1, Y&#x2267;1, Z&#x2267;1) is provided. An RF power is provided to form the etch gas into a plasma, wherein the silicon nitride is exposed to the plasma.

Highly selective oxygen free silicon nitride etch

An all-in-one trench-over-via etch wherein etching of a low-k material beneath a metal hard mask of titanium nitride containing material is carried out in alternating steps of (a) etching the low-k material while maintaining chuck temperature at about 45 to 80&#xb0; C. and (b) metal hard mask rounding and Ti-based residues removal while maintaining chuck temperature at about 90 to 130&#xb0; C.

Pulsed dielectric etch process for in-situ metal hard mask shape control to enable void-free metallization

A multi-step etch process wherein elliptical via openings and trench openings are formed in a dielectric layer includes supporting a multi-layer film stack on a temperature controlled electrostatic chuck in a plasma etch reactor. The multi-layer film stack has a dielectric layer and a patterned metal hard mask layer above the dielectric layer. An etchant gas is supplied to the plasma etch reactor. The etchant gas is energized into a plasma state, and via openings in a photo resist are transferred into a planarization layer and then into elliptical portions of the trench openings in a patterned hard mask layer while maintaining the chuck at a temperature of about 30 to 50&#xb0; C. The elliptical openings are extended into a lower layer of the hard mask and into an underlying dielectric layer while maintaining the chuck at a temperature of 20&#xb0; C. or below. After stripping the planarization layer to expose the trench pattern in the hard mask, trench openings are formed in the dielectric layer while maintaining the chuck at a temperature of about 55&#xb0; C. or higher. The process can thus provide enlarged via contact areas while etching trenches with pitches of 80 nm or less.

Method of etching self-aligned vias and trenches in a multi-layer film stack

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Cohoes, NY, United States of America

Bhaskar Nagabhirava