Globalfoundries Inc.

Globalfoundries U.S. Inc.

Bharat V Krishnan

Jinping Liu

Bongki Lee

Shishir K Ray

Jiehui Shu

Rinus Tek Po Lee

Joseph K Kassim

Hui Zang

Jody Alan Fronheiser

Rishikesh Krishnan

Timothy James McArdle

Seung Yeon Kim

Weihua Tong

Vidmantas Sargunas

Min-Hwa Chi

Andy C Wei

Guillaume Bouche

Huang Liu

Haigou Huang

Murat Kerem Akarvardar

Jin Ping Liu

Yiheng Xu

Joseph Francis Shepard, Jr

Zhao Lun

Huy Cao

Xintuo Dai

Akshey Sehgal

Matthew W Stoker

Tek Po Rinus Lee

Qun Gao

Haifeng Sheng

Hui Zhan

Chang Ho Maeng

Annie Levesque

Fuad H Al-Amoody

Kenneth Andrew Bates

Shyam Pal

Churamani Gaire

Robert Judson Holt

Curtis Durfee

Hyung Yoon Choi

Rinus T P Lee

Meera S Mohan

Anthony Ozzello

Ja-Hyung Han

SangWoo Lim

Disclosed are a method of forming a fin-type field effect transistor (FINFET) and a FINFET structure. In the method, isolation regions are formed on opposing sides of a semiconductor fin. Each isolation region is shorter than the fin, has a lower isolation portion adjacent to a lower fin portion, and has an upper isolation portion that is narrower than the lower isolation portion and separated from a bottom section of an upper fin portion by a space. Surface oxidation of the upper fin portion thins the top section, but leaves the bottom section relatively wide. During gate formation, the gate dielectric layer fills the spaces between the bottom section of the upper fin portion and the adjacent isolation regions. Thus, the gate conductor layer is formed above any fin bulge area and degradation of gate control over the channel region due to a non-uniform fin width is minimized or avoided.

Fin-type field effect transistor with reduced fin bulge and method

The present disclosure relates to semiconductor structures and, more particularly, to multiple threshold voltage devices and methods of manufacture. The structure includes: a gate dielectric material; a gate material on the gate dielectric material, the gate material comprising different thickness in different regions each of which are structured for devices having a different Vt; and a workfunction material on the gate material.

Multiple threshold voltage devices

A device including a triple-layer EPI stack including SiGe, Ge, and Si, respectively, with Ga confined therein, and method of production thereof. Embodiments include an EPI stack including a SiGe layer, a Ge layer, and a Si layer over a plurality of fins, the EPI stack positioned between and over a portion of sidewall spacers, wherein the Si layer is a top layer capping the Ge layer, and wherein the Ge layer is a middle layer capping the SiGe layer underneath; and a Ga layer in a portion of the Ge layer between the SiGe layer and the Si layer.

Device with highly active acceptor doping and method of production thereof

Methods of forming a fin-type field-effect transistor. A gate structure is formed that extends across a plurality of semiconductor fins. A spacer layer composed of a dielectric material is conformally deposited over the gate structure, the semiconductor fins, and a dielectric layer in gaps between the semiconductor fins. A protective layer is conformally deposited over the spacer layer. The protective layer over the dielectric layer in the gaps between the semiconductor fins is masked, and the protective layer is then removed from the gate structure and the semiconductor fins selective to the dielectric material of the spacer layer.

Protected trench isolation for fin-type field-effect transistors

An insulator is formed by flowable chemical vapor deposition (FCVD) process. The insulator is cured by exposing the insulator to ultraviolet light while flowing ozone over the insulator to produce a cured insulator. The curing process forms nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters in the insulator. Following the curing process, these methods select wavelengths of microwave radiation (that will be subsequently used during annealing) so that such wavelengths excite the nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters. Then, these methods anneal the cured insulator by exposing the cured insulator to microwave radiation in an inert (e.g., non-oxidizing) ambient atmosphere, at a temperature below 500&#xb0; C., so as to increase the density of the cured insulator.

Microwave annealing of flowable oxides with trap layers

The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.

FinFETs with strained channels and reduced on state resistance

One aspect of the disclosure is directed to a method of forming a semiconductor structure. The method including: removing each fin in a set of fins from between insulator pillars to expose a portion of a substrate between each insulator pillar, the substrate having a first device region and a second device region; forming a first material over the exposed portions of the substrate between each insulator pillar, the first material including a two-dimensional material; forming a second material over the first material in the first device region, the second material including a first three-dimensional bonding material; and forming a third material over the exposed first material in the second device region, the third material including a second three-dimensional bonding material.

Semiconductor structure including two-dimensional and three-dimensional bonding materials

Disclosed are methods of forming field effect transistor(s) (FET) and the resulting structures. Instead of forming the FET source/drain (S/D) regions during front end of the line (FEOL) processing, they are formed during middle of the line (MOL) processing through metal plug openings in an interlayer dielectric (ILD) layer. Processes used to form the S/D regions through the metal plug openings include S/D trench formation, epitaxial semiconductor material deposition, S/D dopant implantation and S/D dopant activation, followed by silicide and metal plug formation. Since the post-MOL processing thermal budget is low, the methods ensure reduced S/D dopant deactivation, reduced S/D strain reduction, and reduced S/D dopant diffusion and, thus, enable reduced S/D resistance, optimal strain engineering, and flexible junction control, respectively. Since the S/D regions are formed through the metal plug openings, the methods eliminate overlay errors that can lead to uncontacted or partially contacted S/D regions.

Field effect transistors with reduced parasitic resistances and method

Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiOlayer; forming a metal layer over the SiOlayer; and planarizing the metal and SiOlayers down to the gate cap layer.

Siloxane and organic-based MOL contact patterning

A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.

Forming defect-free relaxed SiGe fins

Integrated circuits and methods for producing the same are provided. In accordance with one embodiment a method of producing an integrated circuit includes forming a trench defined by a first material. The trench is filled with a second material to produce a gap defined within the second material, where the second material is in a solid state. The second material is reflowed within the trench to reduce a volume of the gap, and the second material is then solidified within the trench.

Integrated circuits and methods for their fabrication

Methods are providing for fabricating transistors having at least one source region or drain region with a stressed portion. The methods include: forming, within a cavity of a substrate structure, the at least one source region or drain region with the internal stress; and resurfacing the at least one source region or drain region to reduce surface defects of the at least one source region or drain region without relaxing the stressed portion thereof. For instance, the resurfacing can include melting an upper portion of the at least one source region or drain region. In addition, the resurfacing can include re-crystallizing an upper portion of the at least one source region or drain region, and/or providing the at least one source region or drain region with at least one {111} surface.

Fabricating transistors having resurfaced source/drain regions with stressed portions

Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method is provided for fabricating an integrated circuit. The method includes forming a first FET trench in a first FET region and a second FET trench in a second FET region of an interlayer dielectric material on a semiconductor substrate, at least partially filling the first and second FET trenches with a work function metal to form a work function metal layer, and at least partially removing a portion of the work function metal layer in the second FET trench. The first FET trench is defined as an NFET trench and the second FET trench is defined as a PFET trench.

Methods of fabricating integrated circuits

Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a first fin structure overlying a first type region in a semiconductor substrate and forming a second fin structure overlying a second type region in the semiconductor substrate. A gate is formed overlying each fin structure and defines a channel region in each fin structure. The method includes masking the second type region and etching the first fin structure around the gate in the first fin structure to expose the channel region in the first fin structure. Further, the method includes doping the channel region in the first fin structure, and forming source/drain regions of the first fin structure around the channel region in the first fin structure.

Integrated circuits having finFETs with improved doped channel regions and methods for fabricating same

Growing community of inventors

Mechanicville, NY, United States of America

Bharat V Krishnan