Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Bhagwati Prasad

Alan Kalitsov

Derek Stewart

Bruce David Terris

Raghuveer S Makala

Rahul Sharangpani

Matthew Joseph Carey

Tiffany Santos

Joyeeta Nag

Adarsh Rajashekhar

Fei Zhou

Neil Smith

Goran Mihajlovic

Seung-Yeul Yang

Kartik Sondhi

Lei Wan

Kumar Srinivasan

Wonjoon Jung

Rajesh Chopdekar

A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

Memory device containing composition-controlled ferroelectric memory elements and method of making the same

A memory device includes a first electrode, a second electrode, and a magnetic tunnel junction located between the first electrode and the second electrode. The magnetic tunnel junction includes a reference layer, a free layer, a nonmagnetic tunnel barrier layer located between the reference layer and the free layer, and a platinum-containing layer containing platinum and at least one element selected from iridium, hafnium or ruthenium. The platinum-containing layer contacts the free layer.

Voltage controlled magnetic anisotropy (VCMA) memory devices including platinum containing layer in contact with free layer

A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.

Ferroelectric field effect transistors having enhanced memory window and methods of making the same

A magnetoelectric memory device includes a magnetic tunnel junction located between a first electrode and a second electrode. The magnetic tunnel junction includes a reference layer, a nonmagnetic tunnel barrier layer, a free layer, and a dielectric capping layer. At least one layer that provides voltage-controlled magnetic anisotropy is provided within the magnetic tunnel junction, which may include a pair of nonmagnetic metal dust layers located on, or within, the free layer, or a two-dimensional metal compound layer including a compound of a nonmagnetic metallic element and a nonmetallic element.

Voltage-controlled magnetic anisotropy memory device including an anisotropy-enhancing dust layer and methods for forming the same

Magnetoelectric or magnetoresistive memory cells may include a plurality of reference layers and optionally a plurality of free layers to enhance the tunneling magnetoresistance (TMR) ratio.

Magnetoresistive memory device including a plurality of reference layers

An antiferroelectric memory device includes at least one antiferroelectric memory cell. Each of the at least one antiferroelectric memory cell includes a first electrode, a second electrode and a stack containing an antiferroelectric layer and a doped semiconductor layer or a ferroelectric layer located between the first and the second electrodes.

Antiferroelectric memory devices and methods of making the same

A magnetoresistive memory device includes a first electrode, a second electrode that is spaced from the first electrode, and a perpendicular magnetic tunnel junction layer stack located between the first electrode and the second electrode. The perpendicular magnetic tunnel junction layer stack includes, from one side to another: a reference layer having a fixed reference magnetization direction, a first spinel layer located including a first polycrystalline spinel material having () texture along an axial direction that is perpendicular to an interface with the reference layer, a magnesium oxide layer including a polycrystalline magnesium oxide material having () texture along the axial direction, a second spinel layer including a second polycrystalline spinel material having () texture along the axial direction, and a ferromagnetic free layer.

Spinel containing magnetic tunnel junction and method of making the same

A magnetoresistive memory device includes a magnetic tunnel junction including a free layer, at least two tunneling dielectric barrier layers, and at least one metallic quantum well layer. The quantum well layer leads to the resonant electron tunneling through the magnetic tunnel junction in such a way that it strongly enhances the tunneling probability for one of the magnetization states of the free layer, while this tunneling probability remains much smaller in the opposite magnetization state of the free layer. The device can be configured in a spin transfer torque device configuration, a voltage-controlled magnetic anisotropy, a voltage controlled exchange coupling device configuration, or a spin-orbit-torque device configuration.

Magnetic tunnel junction memory devices employing resonant tunneling and methods of manufacturing the same

Magnetoelectric or magnetoresistive memory cells include a magnesium containing nonmagnetic metal dust layer located between a free layer and a dielectric capping layer.

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San Jose, CA, United States of America

Bhagwati Prasad