Applied Materials, Inc.

Betty Tang

David Wingto Cheung

Gerald Z Yin

Wai-Fan Yau

Yunsang Kim

Farhad K Moghadam

Judy H Huang

Claes H Bjorkman

Kuowei Liu

Dennis J Yost

Hongquing Shan

Nasreen Gazala Chapra

Min Melissa Yu

Jian Ding

Melissa Min Yu

A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.

Integrated low k dielectrics and etch stops

Integrated low K dielectrics and etch stops

A dielectric etch process applicable etching a dielectric layer with an underlying stop layer. It is particularly though not necessarily applicable to forming a dual-damascene interconnect structure by a counterbore process, in which a deep via is etched prior to the formation of a trench connecting two of more vias. A single metallization fills the dual-damascene structure. The substrate is formed with a lower stop layer, a lower dielectric layer, an upper stop layer, and an upper dielectric layer. For example, the dielectric layers may be silicon dioxide, and the stop layers, silicon nitride. The initial deep via etch includes at least two substeps. A first substep includes a non-selective etch through the upper stop layer followed by a second substep of selectively etching through the lower dielectric layer and stopping on the lower stop layer. The first substep may be preceded by yet another substep including a selective etch part ways through the upper dielectric layer. For the oxide/nitride compositions, the selective etch is based on a fluorocarbon and argon chemistry, preferably with a lean etchant of CHF combined with a polymer former, such as C F , C F , or CH F , and the non-selective etch includes a fluorocarbon or hydrocarbon, argon and an oxygen-containing gas, such as CO. The counterbore etch is preferably performed in a high-density plasma reactor which allows the plasma source region to be powered separately from a sheath bias located adjacent to the wafer pedestal.

Plasma etch process in a single inter-level dielectric etch

A dielectric etch process particularly applicable to forming a dual-damascene interconnect structure by a counterbore process, in which a deep via is etched prior to the formation of a trench connecting two of more vias. A single metallization fills the dual-damascene structure. The substrate is formed with a lower stop layer, a lower dielectric layer, an upper stop layer, and an upper dielectric layer. For example, the dielectric layers may be silicon dioxide, and the stop layers, silicon nitride. The initial deep via etch includes at least two substeps. A first substep includes a non-selective etch through the upper stop layer followed by a second substep of selectively etching through the lower dielectric layer and stopping on the lower stop layer. The first substep may be preceded by yet another substep including a selective etch part ways through the upper dielectric layer. For the oxide/nitride compositions, the selective etch is based on a fluorocarbon and argon chemistry, preferably with a lean etchant of CHF,combined with a polymer former, such as C,F,, C,F,, or CH,F,, and the non-selective etch includes a fluorocarbon or hydrocarbon, argon and an oxygen-containing gas, such as CO. The counterbore etch is preferably performed in a high-density plasma reactor which allows the plasma source region to be powered separately from a sheath bias located adjacent to the wafer pedestal.

Counterbore dielectric plasma etch process particularly useful for dual damascene

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San Jose, CA, United States of America

Betty Tang