Imec Vzw

Vrije Universiteit Brussel

Bertrand Parvais

Veeresh Vidyadhar Deshpande

Nadine Collaert

Gaspard Hiblot

Barend Wilhelmus Marinus Van Liempd

A method for forming a heterojunction bipolar transistor is provided. The method includes (a) forming a doped region in a group IV semiconductor layer of a substrate; (b) forming an epitaxially grown III-V semiconductor body on a surface portion of the doped region, the body extending from the surface portion and protruding vertically above the doped region, wherein the doped region and the body forms a first sub-collector part and a second sub-collector part, respectively; and (c) forming an epitaxially grown III-V semiconductor layer stack on the body, the layer stack comprising a collector, a base and an emitter. There is further provided a heterojunction bipolar transistor device.

Method for forming a heterojunction bipolar transistor and a heterojunction bipolar transistor device

Example embodiments relate to low-temperature voltage references using Coulomb blockade mechanisms. One embodiment includes a method of generating a reference voltage. The method includes providing a first single-electron transistor (SET) and a second SET connected in series. The method also includes biasing the first SET and the second SET using a same biasing current (I). Further, the method includes operating the first SET at a slope of a first Coulomb peak and the second SET at a slope of a second Coulomb peak. The slope of the first Coulomb peak and the second Coulomb peak are of the same slope type selected from a rising slope, a peak maximum, and a falling slope. The second Coulomb peak is different from the first Coulomb peak. Additionally, the method includes generating the reference voltage (V) based on a difference between gate-to-source voltages of the first SET (V) and the second SET (V).

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Nil-Saint-Vincent, Belgium

Bertrand Parvais