Infineon Technologies Austria Ag

Infineon Technologies Ag

Bernd Schmoelzer

Edward Fuergut

Ralf Otremba

Teck Sim Lee

Martin Gruber

Uwe Kirchner

Chii Shang Hong

Wolfgang Scholz

Fabian Schnoy

Amirul Afiq Hud

Mark Thomas

Ivan Nikitin

Lee Shuang Wang

Ke Yan Tean

Franz Stueckler

Herbert Hopfgartner

Guenther Lohmann

Felix Grawert

Achim Althaus

Marco Nicolas Mueller

Petteri Palm

Klaus Schiess

Xaver Schloegel

Matteo-Alessandro Kutschak

Daniel Pedone

Edward Fürgut

Peter Luniewski

Mei Fen Hiew

Hwee Yin Low

Joon Shyan Tan

Julian Treu

Li Fong Chong

Yee Beng Daryl Yeow

A semiconductor package is disclosed. In one example, the semiconductor package includes a package body. A first diepad is at least partially uncovered by the package body at the first main surface. A second diepad is at least partially uncovered by the package body at the first main surface. A first semiconductor chip is arranged on the first diepad. A second semiconductor chip is arranged on the second diepad. The semiconductor package further includes at least one lead protruding out of the package body at the side surface. A first groove is formed in the first main surface, wherein the first groove is arranged between the first diepad and the second diepad, and a second groove is formed in the first main surface, wherein the second groove is arranged between the at least one lead and at least one of the first diepad and the second diepad.

Semiconductor packages including a package body with grooves formed therein

A semiconductor package comprising a substrate, at least one semiconductor die disposed on the substrate, at least one electrical connector connected with the semiconductor die, an encapsulant covering the substrate, the at least one semiconductor die, and at least partially the electrical connector, the encapsulant comprising a recess formed into a main surface of the encapsulant, wherein the at least one electrical connector is exposed within the recess.

Semiconductor package comprising a cavity with exposed contacts and a semiconductor module

A method for fabricating a semiconductor device includes: providing a die carrier; disposing a semiconductor die on a main face of the die carrier, the semiconductor die having one or more contact pads; applying an encapsulant at least partially to the semiconductor die and at least a portion of the main face of the die carrier; applying an insulation layer to the encapsulant; and fabricating electrical interconnects by forming openings into the encapsulant and the insulation layer and filling a conductive material into the openings. Additional methods for fabricating a semiconductor device are described.

Method for fabricating a semiconductor device including an embedded semiconductor die

A stacked module arrangement includes: a first molded electronic module; a second molded electronic module; and an interface by which the first molded electronic module and the second molded electronic module are physically and electrically connected to one another in a stacked configuration. The first molded electronic module is a power electronic module having a maximum breakdown voltage of at least 40V and a maximum DC current of at least 10 A.

Stacked module arrangement

A method includes providing a first lead frame that includes a first die pad and a first row of leads, providing a connection lug, mounting a first semiconductor die on the first die pad, the first semiconductor die including first and second voltage blocking terminals, electrically connecting the connection lug to one of the first and second voltage blocking terminals, electrically connecting a first one of the leads from the first row to an opposite one of the first and second voltage blocking terminals, and forming an encapsulant body of electrically insulating material that encapsulates first die pad and the first semiconductor die. After forming the encapsulant body, the first row of leads each protrude out of a first outer face of the encapsulant body and the connection lug protrudes out of a second outer face of the encapsulant body.

Method of forming a semiconductor package with connection lug

A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.

Package with electrically insulated carrier and at least one step on encapsulant

A semiconductor device module includes a package carrier having an opening, wherein in the opening there is disposed a semiconductor package including a semiconductor die, an encapsulant, and first vertical contacts, wherein the encapsulant at least partially covers the semiconductor die, and the first vertical contacts are connected to the semiconductor die and extend at least partially through the encapsulant, and a first outer metallic contact layer electrically connected to the first vertical contacts.

Semiconductor device module having vertical metallic contacts and a method for fabricating the same

A semiconductor device includes a die carrier, a semiconductor die disposed on a main face of the die carrier, the semiconductor die including one or more contact pads, an encapsulant covering at least partially the semiconductor die and at least a portion of the main face of the die carrier, an insulation layer covering the encapsulant, and one or more electrical interconnects, each being connected with one of the one or more contact pads of the semiconductor die and extending through the encapsulant.

Semiconductor device including an embedded semiconductor die

A package for mounting on a mounting base is disclosed. In one example, the package comprises a carrier, an electronic component mounted at the carrier, leads electrically coupled with the electronic component and to be electrically coupled with the mounting base, and a linear spacer for defining a spacing with respect to the carrier.

Linear spacer for spacing a carrier of a package

A semiconductor package includes a first die pad, a first semiconductor die mounted on the first die pad, an encapsulant body of electrically insulating material that encapsulates first die pad and the first semiconductor die, a plurality of package leads that each protrude out of a first outer face of the encapsulant body, a connection lug that protrudes out of a second outer face of the encapsulant body, the second outer face being opposite from the first outer face. The first semiconductor die includes first and second voltage blocking terminals. The connection lug is electrically connected to one of the first and second voltage blocking terminals of the first semiconductor die. A first one of the package leads is electrically connected to an opposite one of the first and second voltage blocking terminals of the first semiconductor die that the first connection lug is electrically connected to.

Semiconductor package with connection lug

In an embodiment, an assembly includes an electronic component, a fixing member, a resilient member and a substrate having a first surface. The electronic component includes a heat-generating semiconductor device, a die pad and a plastic housing. The heat-generating semiconductor device is mounted on a first surface of the die pad, and the die pad is at least partially embedded in the plastic housing. The resilient member is engaged under compression between an upper side of the electronic component and a lower surface of the fixing member and the fixing member secures the electronic component to the first surface of the substrate.

Assembly and method for mounting an electronic component to a substrate

A power semiconductor arrangement includes a carrier and packages. Each package: encloses a power semiconductor die having first and second load terminals and configured to conduct a die load current between the load terminals; has a package body with a top side, a footprint side and sidewalls extending from the footprint side to the top side; a lead frame structure configured to electrically and mechanically couple the package to the carrier with the package footprint side facing the carrier, the lead frame structure including at least one first outside terminal electrically connected with the first load terminal of the die; a top layer arranged at the package top side and electrically connected with the second load terminal of the die. A top heatsink is attached to each package top layer, electrically contacted to each package top layer, and configured to conduct at least a sum of the die load currents.

Multi-package top-side-cooling

A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first and second load terminals for blocking a blocking voltage. A lead frame structure electrically and mechanically couples the package to a support and includes an outside terminal extending out of the package footprint side and/or the sidewalls, and is electrically connected with the first load terminal. A top layer arranged at the package top side is electrically connected with the second load terminal. A creepage length between the electrical potential of the outside terminal and the electrical potential of the top layer is defined by a package body surface contour. The surface contour is formed at least by the package top side and package sidewall. At least one structural feature also forms the surface contour is configured to increase the creepage length.

SMD package with top side cooling

A device may include a carrier, a semiconductor chip arranged over a first surface of the carrier, and an encapsulation body comprising six side surfaces and encapsulating the semiconductor chip. A second surface of the carrier opposite to the first surface of the carrier is exposed from the encapsulation body. The device may further include electrical contact elements electrically coupled to the semiconductor chip and protruding out of the encapsulation body exclusively through two opposing side surfaces of the encapsulation body which have the smallest surface areas of all the side surfaces of the encapsulation body, and an electrically insulating layer arranged over the exposed second surface of the carrier.

Growing community of inventors

Radenthein, Austria

Bernd Schmoelzer