International Business Machines Corporation

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Bernard S Meyerson

Alfred Grill

Jack Oon Chu

John Albrecht Ott

Vishnubhai Vitthalbhai Patel

Robert Rosenberg

Johannes M Stork

Wilbur David Pricer

Thomas Benjamin Faure

Basanth Jagannathan

Bruce A Scott

Yuan-Chen Sun

Emmanuel F Crabbe

Sophie Verdonckt-Vandebroek

Robert H Dennard

Tze-Chiang Chen

David Louis Harame

Karen A Nummy

Thomas James Heller, Jr

Khalid EzzEldin Ismail

Denny D Tang

Michael Ignatowski

Ernest Bassous

Martin Revitz

James Walter Rymarczyk

Pong-Fei Lu

Russell C Lange

Egidio E Marotta

Kevin J Uram

Nanik Bakhru

Jeffrey L Blouse

Inge G Fulton

Basanth Jaqannathan

Cecilia C Smolinski

Francoise Kolmer Legoues

Rajiv V Joshi

Cheng Tzong Horng

Gary Bela Bronner

Michael John Brady

Mark A Jaso

Frank F Fang

John Acocella

Joachim Norbert Burghartz

James H Comfort

Thomas F Kuech

Gary L Patton

Michael A Russak

Gregory Scott Hopper

Marc H Brodsky

William J Nestork

John M Warlaumont

Paul M Fahey

Joseph M Jasinski

Wilber D Pricer

John R Turnbull, Jr

Donald J Wolford, Jr

Janes H Comfort

Paul B Jones

Emmanuel Crabbe'

Richard M Plecenik

A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350&#xb0; C. to 750&#xb0; C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon &#x3c;10cm, the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850&#xb0; C. and rapid thermal anneal temperatures to 1000&#xb0; C.

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A method, system, and computer program product are disclosed for dynamically managing power in a microprocessor chip that includes physical hardware elements within the microprocessor chip. A process is selected to be executed. Hardware elements that are necessary to execute the process are then identified. The power in the microprocessor chip is dynamically altered by altering a present power state of the hardware elements that were identified as being necessary.

System and computer program product for dynamically managing power in microprocessor chips according to present processing demands

Method for dynamically managing power in microprocessor chips according to present processing demands

A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350&#xb0; C. to 750&#xb0; C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitakial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon &#x3c;10cm, the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850&#xb0; C. and rapid thermal anneal temperatures to 1000&#xb0; C.

Epitaxial and polycrystalline growth of Si1-x-yGexCy and Si1-yCy alloy layers on Si by UHV-CVD

A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350&deg; C. to 750&deg; C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon <10 cm , the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850&deg; C. and rapid thermal anneal temperatures to 1000&deg; C.

A MISFET having a graded semiconductor alloy channel layer of silicon germanium in which the germanium is graded to a single peak percentage level. The single peak percentage level defines the location of the charge carriers within the layer. The transconductance of the device can be optimized by controlling the location of the carriers within the channel.

Method of making graded channel effect transistor

A method and apparatus for depositing single crystal, epitaxial films of silicon on a plurality of substrates in a hot wall, isothermal deposition system is described. The deposition temperatures are less than about 800.degree. C., and the operating pressures during deposition are such that non-equilibrium growth kinetics determine the deposition of the silicon films. An isothermal bath gas of silicon is produced allowing uniform deposition of epitaxial silicon films simultaneously on multiple substrates. This is a flow system in which means are provided for establishing an ultrahigh vacuum in the range of about 10.sup.-9 Torr prior to epitaxial deposition. The epitaxial silicon layers can be doped in-situ to provide very abruptly defined regions of either n- or p-type conductivity.

Method and apparatus for low temperature, low pressure chemical vapor

Graded channel field effect transistor

A multi-layered structure and process for forming it arc described, incorporating a single crystal substrate, a plurality of epitaxial layers having graded composition wherein the layers have changing lattice spacings not exceeding about 2 percent per 1000 .ANG. of thickness whereby misfit dislocations are formed to relieve strain and then move to the edges of respective layers. The invention overcomes the problem of large numbers of misfit dislocations threading to the surface of the top layer, especially during device processing at temperatures in a range from 700 to 900 degrees Celsius. Fully relaxed, incommensurate structures having low defect densities are obtained, where arbitrary combinations of materials can be used.

Low defect density/arbitrary lattice constant heteroepitaxial layers

A dual transistor CMOS inverter can be built wherein a single gate is shared by two MOS transistors but only one transistor can be turned on at a time. A CMOS inverter function is provided. Further, a dual transistor logic function is described incorporating a combination of a lateral bipolar transistor (LBT) and a metal-oxide-semiconductor transistor (MOST). The gate of the MOST is used to turn on and off the base of the LBT. When the base is turned on, the LBT is turned on and off depending on the base voltage. This device has, thus, two inputs and can perform logic functions such as OR or NAND, which would typically require four transistors. The invention solves the problem of device density to perform logic by forming stacked devices with shared electrodes.

Single-transistor logic and CMOS inverters

A junction field effect transistor and method for making is described incorporating horizontal semiconductor layers within an opening to form a channel and a semiconductor layer through which the opening was made which forms a gate electrode surrounding the channel. The horizontal semiconductor layers may be a SiGe alloy with graded composition near the source and drain. The invention overcomes the problem of forming low resistance JFET's and provides a gate length that is easily scaleable to submicron dimensions for rf, microwave, millimeter and logic circuits without short channel effects.

Si/SiGe vertical junction field effect transistor

A multi-layered structure and process for forming it are described, incorporating a single crystal substrate, a plurality of epitaxial layers having graded composition wherein the layers have changing lattice spacings not exceeding about 2 percent per 1000 .ANG. of thickness whereby misfit dislocations are formed to relieve strain and then move to the edges of respective layers. The invention overcomes the problem of large numbers of misfit dislocations threading to the surface of the top layer, especially during device processing at temperatures in a range from 700 to 900 degrees Celsius. Fully relaxed, incommensurate structures having low defect densities are obtained, where arbitrary combinations of materials can be used.

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Yorktown Heights, NY, United States of America

Bernard S Meyerson