Sgs-thomson Microelectronics S.a.

Commissariat a L'energie Atomique

Stmicroelectronics S.a.

Stmicroelectronics (crolles 2) Sas

Stmicroelectronics (grenoble) Sas

Commissariat À L'énergie Atomique Et Aux Énergies Alternatives Centre National De La Recherche Scientifique

Centre National De La Recherche Scientifique

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Stmicroelectronics (rousset) Sas

Bernard Guillaumot

Constantin Papadas

Philippe Coronel

Emilie Bernard

Simon Deleonibus

Roch Espiau De Lamaestre

Jean-Jacques Greffet

Christian Vizioz

Ruben Esteban Llorente

A source of photons resulting from a recombination of localized excitons, including a semiconductor layer having a central portion surrounded with heavily-doped regions; above said central portion, a layer portion containing elements capable of being activated by excitons, coated with a first metallization; and under the semiconductor layer, a second metallization of greater extension than the first metallization. The distance between the first and second metallizations is on the order of from 10 to 60 nm; and the lateral extension of the first metallization is on the order of from &#x3bb;0/10*nto &#x3bb;0/2*n, where &#x3bb;0 is the wavelength in vacuum of the emitted light and nis the effective refractive index of the mode formed in the cavity created by the two metallizations.

Source of photons resulting from a recombination of localized excitons

A semiconductor device includes a semiconductor channel region and a gate region, wherein the gate region includes at least one buried part extending under the channel region. The buried part of the gate region is formed from a cavity under the channel region. The cavity is filled with a first material. An opening is made to access the first material. In one implementation, aluminium is deposited in the opening in contact with the first material. An anneal is performed to cause the aluminium to be substituted for the first material in the cavity. In another implementation, a second material different from the first material is deposited in the opening. An anneal is performed to cause an alloy of the first and second materials to be formed in the cavity.

Method of manufacturing a buried-gate semiconductor device and corresponding integrated circuit

A semiconductor device includes a semiconductive channel region and a gate region. The gate region has at least one buried part extending under the channel region. The buried part of the gate region is formed by forming a cavity under the channel region. That cavity is at least partial filled with silicon and a metal. An annealing step is performed so as to form a silicide of said metal in the cavity. The result is a totally silicided buried gate for the semiconductor device.

Method of fabricating a buried-gate semiconductor device and corresponding integrated circuit

An electronic memory having a source () and a drain () comprising on a substrate () a floating gate () and a control gate (). According to the invention, the floating gate () has a substantially U-shaped cross-section defining a space within which the control gate () is arranged.

Damascene architecture electronic storage and method for making same

A four state programmable memory cell includes a substrate of a first conductivity type having a channel region having a first side and a second side, a control gate located on a first insulating layer above the channel region, a drain region of a second conductivity type located on the substrate adjacent to the first side of the channel region, a source region of a second conductivity type located on the substrate adjacent to the second side of the channel region, a first insulated floating gate located on a second insulating layer above the drain region adjacent to the control gate, and a second insulated floating gate located on a third insulating layer above the source region adjacent to the control gate.

Electrically programmable memory cell

An electrically programmable cell comprises a substrate of the first conductivity type having a channel region, a control gate on a first insulating layer above the channel region, a source region and a drain region of a second conductivity type, on both sides of the channel region, at least the drain region including a low-doped region adjacent to the channel, a floating gate on a second insulating layer above at least a portion of said low-doped region. The thickness of the second insulating layer is lower than the thickness of the first insulating layer and is low enough for having charge transfers through tunnel effect.

Growing community of inventors

Le Fontanil, France

Bernard Guillaumot